PDM31548SA10A 데이터 시트보기 (PDF) - Paradigm Technology

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PDM31548SA10A

128K x 16 CMOS 3.3V Static RAM

Paradigm Technology 

Pin Configuration

TSOP

PRELIMINARY

A4 1

A3 2

A2 3

A1 4

A0 5

CE 6

I/O0 7

I/O1 8

I/O2 9

I/O3 10

Vcc 11

Vss 12

I/O4 13

I/O5 14

I/O6 15

I/O7 16

WE 17

A16 18

A15 19

A14 20

A13 21

A12 22

44 A5

43 A6

42 A7

41 OE

40 UB

39 LB

38 I/O15

37 I/O14

36 I/O13

35 I/O12

34 Vss

33 Vcc

32 I/O11

31 I/O10

30 I/O9

29 I/O8

28 NC

27 A8

26 A9

25 A10

24 A11

23 NC

PDM31548

SOJ

A4 1

A3 2

A2 3

A1 4

A0 5

CE 6

I/O0 7

I/O1 8

I/O2 9

I/O3 10

Vcc 11

Vss 12

I/O4 13

I/O5 14

I/O6 15

I/O7 16

WE 17

A16 18

A15 19

A14 20

A13 21

A12 22

44 A5

43 A6

42 A7

41 OE

40 UB

39 LB

38 I/O15

37 I/O14

36 I/O13

35 I/O12

34 Vss

33 Vcc

32 I/O11

31 I/O10

30 I/O9

29 I/O8

28 NC

27 A8

26 A9

25 A10

24 A11

23 NC

Pin Description

Name

A16-A0

I/O15-I/O0

CE

WE

OE

LB, UB

NC

Vss

VCC

Description

Address Inputs

Data Inputs

Chip Enable Input

Write Enable Input

Output Enable Input

Data Byte Control Inputs

No Connect

Ground

Power (+3.3V)

Capacitance (TA = +25°C, f = 1.0 MHz)

Symbol

Parameter

Conditions

Max.

Unit

CIN

CI/O

NOTE:

Input Capacitance

Output Capacitance

VIN = VSS

VI/O = VSS

6

pF

8

pF

1. This parameter is determined by device characterization, but is not production tested.

2

Rev. 1.3 - 4/13/98

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