MT28F002B3 데이터 시트보기 (PDF) - Micron Technology
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MT28F002B3 Datasheet PDF : 31 Pages
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SMART 3 BOOT BLOCK FLASH MEMORY
FUNCTIONAL DESCRIPTION
The MT28F002B3 and MT28F200B3 flash memory
incorporate a number of features ideally suited for
system firmware. The memory array is segmented into
individual erase blocks. Each block may be erased
without affecting data stored in other blocks. These
memory blocks are read, written and erased with com-
mands to the command execution logic (CEL). The CEL
controls the operation of the internal state machine
(ISM), which completely controls all write, block erase
and verify operations. The ISM protects each memory
location from over-erasure and optimizes each memory
location for maximum data retention. In addition, the
ISM greatly simplifies the control necessary for writing
the device in-system or in an external programmer.
The Functional Description provides detailed infor-
mation on the operation of the MT28F002B3 and
MT28F200B3 and is organized into these sections:
• Overview
• Memory Architecture
• Output (Read) Operations
• Input Operations
• Command Set
• ISM Status Register
• Command Execution
• Error Handling
• Write/Erase Cycle Endurance
• Power Usage
• Power-Up
OVERVIEW
SMART 3 TECHNOLOGY (B3)
Smart 3 technology allows maximum flexibility for
in-system READ, WRITE and ERASE operations. WRITE
and ERASE operations may be executed with a VPP
voltage of 3.3V or 5V. Due to process technology
advances, 5V VPP is optimal for application and produc-
tion programming. For backward compatibility with
SmartVoltage technology, 12V VPP is supported for a
maximum of 100 cycles and may be connected for up
to 100 cumulative hours. However, no performance
increase will be realized. For any operation, VCC is at
3.3V.
FIVE INDEPENDENTLY ERASABLE MEMORY
BLOCKS
The MT28F002B3 and MT28F200B3 are organized
into five independently erasable memory blocks that
allow portions of the memory to be erased without
affecting the rest of the memory data. A special boot
block is hardware-protected against inadvertent era-
sure or writing by requiring either a super-voltage on
the RP# pin or driving the WP# pin HIGH. One of these
two conditions must exist along with the VPP voltage
(3.3V or 5V) on the VPP pin before a WRITE or ERASE
will be performed on the boot block. The remaining
blocks require only the VPP voltage be present on the
VPP pin before writing or erasing.
HARDWARE-PROTECTED BOOT BLOCK
This block of the memory array can be erased or
written only when the RP# pin is taken to VHH or when
the WP# pin is brought HIGH. This provides additional
security for the core firmware during in-system firm-
ware updates should an unintentional power fluctua-
tion or system reset occur. The MT28F002B3 and
MT28F200B3 are available with the boot block starting
at the bottom of the address space (“B” suffix) or the top
of the address space (“T” suffix).
SELECTABLE BUS SIZE (MT28F200B3 ONLY)
The MT28F200B3 allows selection of an 8-bit (256K
x 8) or 16-bit (128K x 16) data bus for reading and
writing the memory. The BYTE# pin is used to select the
bus width. In the x16 configuration, control data is read
or written only on the lower eight bits (DQ0-DQ7).
Data written to the memory array utilizes all active
data pins for the selected configuration. When the x8
configuration is selected, data is written in byte form;
when the x16 configuration is selected, data is written
in word form.
INTERNAL STATE MACHINE (ISM)
BLOCK ERASE and BYTE/WORD WRITE timing are
simplified with an ISM that controls all erase and write
algorithms in the memory array. The ISM ensures
protection against overerasure and optimizes write
margin to each cell.
During WRITE operations, the ISM automatically
increments and monitors WRITE attempts, verifies write
margin on each memory cell and updates the ISM status
register. When BLOCK ERASE is performed, the ISM
automatically overwrites the entire addressed block
(eliminates overerasure), increments and monitors
ERASE attempts, and sets bits in the ISM status register.
ISM STATUS REGISTER
The ISM status register allows an external processor
to monitor the status of the ISM during WRITE and
ERASE operations. Two bits of the 8-bit status register
are set and cleared entirely by the ISM. These bits
indicate whether the ISM is busy with a WRITE or
ERASE task and when an ERASE has been suspended.
Additional error information is set in three other bits:
VPP status, write status and erase status.
2Mb Smart 3 Boot Block Flash Memory
F48.p65 – Rev. 1/00
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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