MCM6341ZP12 데이터 시트보기 (PDF) - Motorola => Freescale
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MCM6341ZP12 Datasheet PDF : 10 Pages
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WRITE CYCLE 2 (E Controlled; See Notes 1, 2, 3, and 4)
MCM6341–10 MCM6341–11 MCM6341–12 MCM6341–15
Parameter
Symbol Min Max Min Max Min Max Min Max Unit Notes
Write Cycle Time
Address Setup Time
Address Valid to End of Write
Address Valid to End of Write (G
High)
tAVAV
10
—
11
—
12
—
15
—
ns
5
tAVEL
0
—
0
—
0
—
0
—
ns
tAVEH
9
—
10
—
10
—
12
—
ns
tAVEH
8
—
9
—
9
—
10
—
ns
Enable Pulse Width
tELEH,
9
—
10
—
10
—
12
—
ns
6, 7
tELWH
Enable Pulse Width (G High)
tELEH,
8
—
9
—
9
—
10
—
ns
6, 7
tELWH
Data Valid to End of Write
tDVEH
4
—
5
—
5
—
6
—
ns
Data Hold Time
tEHDX
0
—
0
—
0
—
0
—
ns
Write Recovery Time
tEHAX
0
—
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
5. All write cycle timing is referenced from the last valid address to the first transitioning address.
6. If E goes low coincident with or after W goes low, the output will remain in a high–impedance condition.
7. If E goes high coincident with or before W goes high, the output will remain in a high–impedance condition.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
WRITE CYCLE 2 (E Controlled; See Notes 1, 2, 3, and 4)
tAVAV
tAVEH
tELEH
tAVEL
tELWH
HIGH–Z
tDVEH
DATA VALID
tEHAX
tEHDX
MCM6341
8
MOTOROLA FAST SRAM
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