IS61NF12836-8.5TQ 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS61NF12836-8.5TQ

128K x 32, 128K x 36 and 256K x 18 FLOW-THROUGH 'NO WAIT' STATE BUS SRAM

Integrated Silicon Solution 

IS61NF12832 IS61NF12836 IS61NF25618

IS61NLF12832 IS61NLF12836 IS61NLF25618

ISSI ®

INTERLEAVED BURST ADDRESS TABLE (MODE = VCC)

External Address

A1 A0

00

01

10

11

1st Burst Address

A1 A0

01

00

11

10

2nd Burst Address

A1 A0

10

11

00

01

3rd Burst Address

A1 A0

11

10

01

00

LINEAR BURST ADDRESS TABLE (MODE = GND)

0,0

A1', A0' = 1,1

0,1

1,0

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Parameter

Value

Unit

TBIAS

TSTG

Temperature Under Bias

Storage Temperature

–10 to +85

°C

–65 to +150

°C

PD

Power Dissipation

1.6

W

IOUT

Output Current (per I/O)

VIN, VOUT Voltage Relative to GND for I/O Pins

100

mA

–0.5 to VCCQ + 0.3 V

VIN

Voltage Relative to GND for

for Address and Control Inputs

–0.3 to 4.6

V

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-

nent damage to the device. This is a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the operational sections of this specifi-

cation is not implied. Exposure to absolute maximum rating conditions for extended periods

may affect reliability.

2. This device contains circuity to protect the inputs against damage due to high static voltages or

electric fields; however, precautions may be taken to avoid application of any voltage higher

than maximum rated voltages to this high-impedance circuit.

3. This device contains circuitry that will ensure the output devices are in High-Z at power up.

8

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00E

05/29/02

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