IS61LP12836-166TQ(2004) 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS61LP12836-166TQ
(Rev.:2004)

128K x 32, 128K x 36 SYNCHRONOUS PIPELINED STATIC RAM

Integrated Silicon Solution 

IS61LP12832

IS61LP12836

128K x 32, 128K x 36 SYNCHRONOUS

PIPELINED STATIC RAM

ISSI®

FEBRUARY 2004

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Linear burst sequence control using MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Common data inputs and data outputs

• JEDEC 100-Pin TQFP and

119-pin PBGA packages

• Power Supply

+3.3V VDD

+3.3V or 2.5V VDDQ (I/O)

• Snooze mode for reduced standby power

• Industrial temperature available

DESCRIPTION

The ISSI IS61LP12832 and IS61LP12836 is a high-speed

synchronous static RAM designed to provide a burstable,

high-performance memory for high speed networking and

communication applications. It is organized as 131,072

words by 32 bits and 36 bits, fabricated with ISSI's

advanced CMOS technology. The device integrates a 2-bit

burst counter, high-speed SRAM core, and high-drive

capability outputs into a single monolithic circuit. All

synchronous inputs pass through registers controlled by

a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be from

one to four bytes wide as controlled by the write control

inputs.

Separate byte enables allow individual bytes to be written.

BW1 controls DQa, BW2 controls DQb, BW3 controls

DQc, BW4 controls DQd, conditioned by BWE being

LOW. A LOW on GW input would cause all bytes to be

written.

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the ADV (burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

FAST ACCESS TIME

Symbol

tKQ

tKC

Parameter

Clock Access Time

Cycle Time

Frequency

-200

-166

Units

3.1

3.5

ns

5

6

ns

200

166

MHz

Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — 1-800-379-4774

1

Rev. A

02/20/04

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