D
B
HIGH–Z
R
W
R
B
D
W
DATA OUT
(Q VALID)
DW
B
HIGH–Z
(DATA IN)
R
KEY:
CURRENT
STATE (n)
ƒ
INPUT
COMMAND
CODE
NEXT STATE
n+1
NOTES:
1. Input command codes (D, W, R, and B) represent control
pin inputs as indicated in the Truth Table.
2. Hold (i.e., CKE sampled high) is not shown simply be-
cause CKE = 1 blocks clock input and therefore, blocks
any state change.
Figure 3. Data I/O State Diagram
STATE
CK
COMMAND
CODE
n
n+1
n+2
n+3
ƒ
DQ
CURRENT
STATE
NEXT
STATE
Figure 4. State Definitions for ZBT RAM State Diagram
MOTOROLA FAST SRAM
MCM63Z737DMCM63Z819
9