MCM63Z818TQ133R 데이터 시트보기 (PDF) - Motorola => Freescale

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MCM63Z818TQ133R

128K x 36 and 256K x 18 Bit Pipelined ZBT™ RAM Synchronous Fast Static RAM

Motorola => Freescale 

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V ± 5%, TA = 0 to 70°C Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)

Parameter

Symbol

Min

Typ

Supply Voltage

VDD

3.135

3.3

I/O Supply Voltage

Input Low Voltage

VDDQ*

3.135

3.3

VIL

– 0.3

—

Input High Voltage

VIH

2

—

Input High Voltage I/O Pins

VIH2

2

—

* VDD and VDDQ are shorted together on the device and must be supplied with identical voltage levels.

VIH

Max

Unit

3.465

V

VDD

V

0.8

V

VDD + 0.3

V

VDDQ + 0.3

V

VSS

VSS – 1.0 V

20% tKHKH (MIN)

Figure 5. Undershoot Voltage

DC CHARACTERISTICS AND SUPPLY CURRENTS

Parameter

Symbol

Min

Typ

Max

Unit Notes

Input Leakage Current (0 V ≤ Vin ≤ VDD)

Ilkg(I)

—

Output Leakage Current (0 V ≤ Vin ≤ VDDQ)

Ilkg(O)

—

AC Supply Current (Device Selected, All Outputs Open,

IDDA

—

Freq = Max) Includes Supply Current for Both VDD and VDDQ

CMOS Standby Supply Current (Device Deselected,

ISB2

—

Freq = 0, VDD = Max, VDDQ = Max, All Inputs Static at CMOS

Levels)

—

±1

µA

1

—

±1

µA

—

350

mA 2, 3, 4

—

5

mA

5, 6

TTL Standby Supply Current (Device Deselected, Freq = 0,

VDD = Max, VDDQ = Max, All Inputs Static at TTL Levels)

ISB3

—

—

25

mA

5, 7

Hold Supply Current (Device Selected, Freq = Max,

IDD1

—

—

15

mA

6

VDD = Max, VDDQ = Max, CKE ≥ VDD – 0.2 V, All Inputs Static at

CMOS Levels)

Output Low Voltage (IOL = 8 mA)

VOL

—

—

0.4

V

Output High Voltage (IOH = – 8 mA)

VOH

2.4

—

—

V

NOTES:

1. LBO has an internal pullup and will exhibit leakage currents of ± 5 µA.

2. Reference AC Operating Conditions and Characteristics for Input and Timing.

3. All addresses transition simultaneously low (LSB) then high (MSB).

4. Data states are all zero.

5. Device in deselected mode as defined by the Truth Table.

6. CMOS levels for I/Os are VIT ≤ VSS + 0.2 V or ≥ VDDQ – 0.2 V. CMOS levels for other inputs are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V.

7. TTL levels for I/O’s are VIT ≤ VIL or ≥ VIH2. TTL levels for other inputs are Vin ≤ VIL or ≥ VIH.

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70°C, Periodically Sampled Rather Than 100% Tested)

Parameter

Symbol

Min

Typ

Input Capacitance

Input/Output Capacitance

Cin

—

4

CI/O

—

7

Max

Unit

5

pF

8

pF

MOTOROLA FAST SRAM

MCM63Z736DMCM63Z818

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