MCM63Z818TQ133R 데이터 시트보기 (PDF) - Motorola => Freescale

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MCM63Z818TQ133R

128K x 36 and 256K x 18 Bit Pipelined ZBT™ RAM Synchronous Fast Static RAM

Motorola => Freescale 

INTERMEDIATE

INTERMEDIATE

D

B

HIGH–Z

R

W

INTERMEDIATE

INTERMEDIATE

R

B

D

W

DATA OUT

(Q VALID)

INTERMEDIATE

DW

B

HIGH–Z

(DATA IN)

R

INTERMEDIATE

KEY:

CURRENT

STATE (n)

INTERMEDIATE

STATE (n + 1)

NEXT STATE

TRANSITION

TRANSITION (n + 2)

ƒ

INPUT

COMMAND

CODE

NOTES:

1. Input command codes (D, W, R, and B) represent control pin

inputs as indicated in the Truth Table.

2. Hold (i.e., CKE sampled high) is not shown simply because

CKE = 1 blocks clock input and therefore, blocks any state

change.

Figure 3. Data I/O State Diagram

STATE

CK

COMMAND

CODE

n

n+1

n+2

n+3

ƒ

DQ

STATE NAME

CURRENT INTERMEDIATE

STATE

STATE

NEXT

STATE

Figure 4. State Definitions for I/O State Diagrams

MOTOROLA FAST SRAM

MCM63Z736DMCM63Z818

9

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