RM5231-150-Q 데이터 시트보기 (PDF) - PMC-Sierra
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RM5231-150-Q Datasheet PDF : 39 Pages
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RM5231™ Microprocessor with 32-bit System Bus Data Sheet
Released
2 Block Diagram
Figure 1 Block Diagram
Primary Data Cache
2-way Set Associative
Store Buffer
Write Buffer
Read Buffer
D Bus
Floating-Point
Load/Align
Floating-Point
Register File
Packer/Unpacker
Floating-Point
MultAdd, Add, Sub,
Cvt, Div, Sqrt
DTag
DTLB
ITag
ITLB
Pad Buffer
Address Buffer
FP Bus
Primary Instruction Cache
2-way Set Associative
A/D Bus
Pad Bus
Instruction Dispatch Unit
FP
Instruction
Register
Integer
Instruction
Register
Integer Bus
Joint TLB
Coprocessor 0
System/Memory
Control
IVA
PC Incrementer
Branch PC Adder
ITLB Virtual
Program Counter
Load Aligner
DVA
Integer Register File
Integer Address/Adder
Shifter/Store Aligner
Logic Unit
FA Bus
DTLB Virtual
PLL/Clocks Int Mult, Div, Madd
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
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Document ID: PMC-2002165, Issue 1
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