MCM6226BBXJ25R2 데이터 시트보기 (PDF) - Motorola => Freescale
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MCM6226BBXJ25R2 Datasheet PDF : 8 Pages
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WRITE CYCLE 1 (W Controlled, See Notes 1, 2, 3, and 4)
6226BB–15 6226BB–17 6226BB–20 6226BB–25 6226BB–35
Parameter
Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes
Write Cycle Time
tAVAV
15 — 17 — 20 — 25 — 35 —
ns
5
Address Setup Time
tAVWL
0
—
0
—
0
—
0
—
0
—
ns
Address Valid to End of Write tAVWH
12 — 14 — 15 — 17 — 20 —
ns
Write Pulse Width
tWLWH, 12 — 14 — 15 — 17 — 20 —
ns
tWLEH
Data Valid to End of Write
tDVWH
7
—
8
—
9
— 10 — 11 —
ns
Data Hold TIme
tWHDX
0
—
0
—
0
—
0
—
0
—
ns
Write Low to Data High–Z
tWLQZ
—
6
—
7
—
7
—
8
—
8
ns 6, 7, 8
Write High to Output Active
tWHQX
5
—
5
—
5
—
5
—
5
—
ns 6, 7, 8
Write Recovery Time
tWHAX
0
—
0
—
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con-
tention conditions during read and write cycles.
3. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.
4. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
5. All timings are referenced from the last valid address to the first transitioning address.
6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b.
7. This parameter is sampled and not 100% tested.
8. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
WRITE CYCLE 1 (W Controlled See Notes 1, 2, 3, and 4)
tAVAV
tAVWH
tWLWH
tWLEH
tAVWL
HIGH–Z
tWLQZ
tDVWH
DATA VALID
HIGH–Z
tWHAX
tWHDX
tWHQX
MOTOROLA FAST SRAM
MCM6226BB
5
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