PM5381 데이터 시트보기 (PDF) - PMC-Sierra
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PM5381 Datasheet PDF : 487 Pages
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PRELIMINARY
DATASHEET
PMC-2000489
ISSUE 1
PMC-Sierra, Inc.
PM5381 S/UNI-2488
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
10.7 RECEIVE CELL AND FRAME PROCESSOR (RCFP)..............................................................................65
10.8 RECEIVE SCALABLE DATA QUEUE (RXSDQ).....................................................................................70
10.9 RECEIVE PHY INTERFACE (RXPHY) .................................................................................................71
10.10 TRANSMIT LINE INTERFACE ..........................................................................................................71
10.11 SONET/SDH TRANSMIT LINE INTERFACE (STLI)..........................................................................72
10.12 TRANSMIT REGENERATOR MULTIPLEXOR PROCESSOR (TRMP) .....................................................72
10.13 TRANSMIT TAIL TRACE PROCESSOR (TTTP) .................................................................................75
10.14 TRANSMIT HIGH ORDER PATH PROCESSOR (THPP)......................................................................76
10.15 TRANSMIT CELL AND FRAME PROCESSOR (TCFP) ........................................................................76
10.16 TRANSMIT SCALABLE DATA QUEUE (TXSDQ) ...............................................................................79
10.17 TRANSMIT PHY INTERFACES (RXPHY AND TXPHY) .....................................................................79
10.18 SONET/SDH BIT ERROR RATE MONITOR (SBER) .......................................................................80
10.19 SONET/SDH ALARM REPORTING CONTROLLER (SARC) .............................................................80
10.20 SONET/SDH INBAND ERROR REPORT PROCESSOR (SIRP).........................................................81
10.21 APS SERIAL DATA INTERFACE ......................................................................................................82
10.22 JTAG TEST ACCESS PORT INTERFACE .........................................................................................83
10.23 MICROPROCESSOR INTERFACE.....................................................................................................83
11 NORMAL MODE REGISTER DESCRIPTION .................................................................................97
12 OPERATION...................................................................................................................................430
12.2 SONET/SDH FRAME MAPPINGS AND OVERHEAD BYTE USAGE ......................................................433
12.3 POS/HDLC DATA STRUCTURE ......................................................................................................438
12.4 SETTING ATM MODE OF OPERATION..............................................................................................439
12.5 SETTING PACKET OVER SONET/SDH MODE OF OPERATION .........................................................439
12.6 BIT ERROR RATE MONITOR............................................................................................................439
12.7 CLOCKING OPERATIONS ................................................................................................................439
12.8 LOOPBACK OPERATION..................................................................................................................439
12.9 BOARD DESIGN RECOMMENDATIONS..............................................................................................440
12.10 POWER SUPPLIES......................................................................................................................440
12.11 INTERFACING TO ECL OR PECL DEVICES...................................................................................440
13 FUNCTIONAL TIMING...................................................................................................................441
13.1
13.2
13.3
13.4
13.5
SERIAL LINE INTERFACE.................................................................................................................441
ATM UTOPIA LEVEL 3 SYSTEM INTERFACE .....................................................................................441
PACKET OVER SONET/SDH (POS) LEVEL 3 SYSTEM INTERFACE..................................................443
SECTION AND LINE DATA COMMUNICATION CHANNELS.....................................................................446
S/UNI-2488 CONCEPTUAL REGIONS .............................................................................................446
14 TEST FEATURES DESCRIPTION.................................................................................................447
15 FUNCTIONAL TIMING...................................................................................................................448
16 ABSOLUTE MAXIMUM RATINGS ................................................................................................449
17 D.C. CHARACTERISTICS .............................................................................................................450
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
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