IS63LV1024-12KI 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS63LV1024-12KI

128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT

Integrated Silicon Solution 

IS63LV1024

ISSI ®

WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)

Symbol

Parameter

-8 ns

-10 ns

-12 ns

-15 ns

Min. Max.

Min. Max.

Min. Max.

Min. Max.

Unit

tWC

Write Cycle Time

8—

10 —

12 —

15 —

ns

tSCE

CE to Write End

7—

7—

8—

10 —

ns

tAW

Address Setup Time to

Write End

8—

8—

8—

10 —

ns

tHA

Address Hold from

Write End

0—

0—

0—

0—

ns

tSA

Address Setup Time

0—

0—

0—

0—

ns

tPWE1(1)

WE Pulse Width (OE High)

7—

7—

8—

10 —

ns

tPWE2(2)

WE Pulse Width (OE Low)

8—

10 —

12 —

15 —

ns

tSD

Data Setup to Write End

5—

5—

6—

7—

ns

tHD

Data Hold from Write End

0—

0—

0—

0—

ns

tHZWE(2)

WE LOW to High-Z Output

—4

—5

—6

—7

ns

tLZWE(2)

WE HIGH to Low-Z Output

3—

3—

3—

3—

ns

Notes:

1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and

output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but

any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of

the signal that terminates the Write.

AC WAVEFORMS

WRITE CYCLE NO. 1(1,2 (CE Controlled, OE = HIGH or LOW)

t WC

ADDRESS

CE

WE

DOUT

DIN

VALID ADDRESS

t SA

t SCE

t HA

DATA UNDEFINED

t AW

t PWE1

t PWE2

t HZWE

HIGH-Z

t LZWE

t SD

t HD

DATAIN VALID

CE_WR1.eps

6

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. H

10/02/00

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