CY7C1345-100AC(2000) 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C1345-100AC
(Rev.:2000)

128K x 36 Synchronous Flow-Through 3.3V Cache RAM

Cypress Semiconductor 

Timing Diagrams

Write Cycle Timing[13, 14]

CY7C1345

CLK

tADS

ADSP

ADSC

ADV

Single W rite

tCYC

tADH

tADS

tADH

tADVS

tADVH

B urst W rite

tCH

Pipelined Write

tCL ADSP ignored with CE1 inactive

ADSC initiated write

Unselected

tAS

ADV Must Be Inactive for ADSP Write

ADD

WD1

WD2

tAH

GW

WE

tWS tWH

tCES tCEH

CE1

tCES

CE2

tCEH

tWH

tWS

CE1 masks ADSP

WD3

Unselected with CE2

CE3

tCES

OE

tCEH

tDH

tDS

Data In High-Z

11aa

2a

2b

= UNDEFINED

2c

2d

3a

= DON’T CARE

High-Z

Notes:

13. WE is the combination of BWE, BW[3:0] and GW to define a write cycle (see Write Cycle Descriptions table).

14. WDx stands for Write Data to Address X.

10

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