CY7C1345-100AC(2000) 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1345-100AC Datasheet PDF : 16 Pages
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CY7C1345
Pin Descriptions
Pin Number Name
85
ADSC
84
ADSP
36, 37
49 −44,
81–82,
99–100,
32–35
96–93
A[1:0]
A[16:2]
BW[3:0]
83
ADV
87
BWE
88
GW
89
CLK
98
CE1
97
CE2
92
CE3
86
OE
64
ZZ
31
MODE
30–28,
25–22,
19–18,
13–12, 9–6,
3–1, 80–78,
75–72,
69–68,
63–62,
59–56,
53–51
15, 41, 65,
91
DQ[31:0],
DP[3:0]
VDD
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Input-
Asynchronous
-
I/O-
Synchronous
Power Supply
Description
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted
LOW, A[15:0] is captured in the address registers. A[1:0] are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted
LOW, A[15:0] is captured in the address registers. A[1:0] are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP
is ignored when CE1 is deasserted HIGH.
A1, A0 Address Inputs. These inputs feed the on-chip burst counter as the LSBs as
well as being used to access a particular memory location in the memory array.
Address Inputs used in conjunction with A[1:0] to select one of the 64K address
locations. Sampled at the rising edge of the CLK, if CE1, CE2, and CE3 are sampled
active, and ADSP or ADSC is active LOW.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes.
Sampled on the rising edge. BW0 controls DQ[7:0] and DP0, BW1 controls DQ[15:8]
and DP1, BW2 controls DQ[23:16] and DP2, and BW3 controls DQ[31:24] and DP3. See
Write Cycle Description table for further details.
Advance Input, used to advance the on-chip address counter. When LOW the inter-
nal burst counter is advanced in a burst sequence. The burst sequence is selected
using the MODE input.
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is
used to conduct a global write, independent of the state of BWE and BW[3:0]. Global
writes override byte writes.
Clock Input. Used to capture all synchronous inputs to the device.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device. CE1 gates ADSP.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins
are three-stated, and act as input data pins.
Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a
low-power standby mode in which all other inputs are ignored, but the data in the
memory array is maintained.Leaving ZZ floating or NC will default the device into an
active state. ZZ pin has an internal pull-down.
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. When left floating or NC,
defaults to interleaved burst order. Mode pin has an internal pull-up.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in
the memory location specified by A[16:0] during the previous clock rise of the read
cycle. The direction of the pins is controlled by OE in conjunction with the internal
control logic. When OE is asserted LOW, the pins behave as outputs. When HIGH,
DQ[31:0] and DP[3:0] are placed in a three-state condition. The outputs are automat-
ically three-stated when a Write cycle is detected.
Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
3
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