CY7C1345-100AC(2000) 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1345-100AC Datasheet PDF : 16 Pages
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CY7C1345
Table 1. Counter Implementation for the Intel
Pentium®/80486 Processor’s Sequence
First
Address
AX + 1, Ax
00
01
10
11
Second
Address
AX + 1, Ax
01
00
11
10
Third
Address
AX + 1, Ax
10
11
00
01
Fourth
Address
AX + 1, Ax
11
10
01
00
Table 2. Counter Implementation for a Linear Sequence
First
Address
AX + 1, Ax
00
01
10
11
Second
Address
AX + 1, Ax
01
10
11
00
Third
Address
AX + 1, Ax
10
11
00
01
Fourth
Address
AX + 1, Ax
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
ICCZZ
tZZS
tZZREC
Description
Snooze mode stand-
by current
Device operation to
ZZ
ZZ recovery time
Test Conditions
ZZ > VDD − 0.2V
ZZ > VDD − 0.2V
ZZ < 0.2V
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ HIGH
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed. Access-
es pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the
duration of tZZREC after the ZZ input returns LOW. Leaving ZZ
unconnected defaults the device into an active state.
Min.
2tCYC
Max.
3
2tCYC
Unit
ns
ns
mA
5
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