M41T80M 데이터 시트보기 (PDF) - STMicroelectronics

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M41T80M

Serial access real-time clock with alarm

STMicroelectronics 

M41T80

2

Operation

Operation

The M41T80 clock operates as a slave device on the serial bus. Access is obtained by

implementing a start condition followed by the correct slave address (D0h). The 20 bytes

contained in the device can then be accessed sequentially in the following order:

● 1st byte: tenths/hundredths of a second register

● 2nd byte: seconds register

● 3rd byte: minutes register

● 4th byte: century/hours register

● 5th byte: day register

● 6th byte: date register

● 7th byte: month register

● 8th byte: year register

● 9th byte: control register

● 10th byte: 32KE bit

● 11th - 16th bytes: alarm registers

● 17th - 19th bytes: reserved

● 20th byte: square wave register

2.1

2.1.1

2.1.2

2.1.3

2-Wire bus characteristics

The bus is intended for communication between different IC’s. It consists of two lines: a bi-

directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be

connected to a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

● Data transfer may be initiated only when the bus is not busy.

● During data transfer, the data line must remain stable whenever the clock line is high.

● Changes in the data line, while the clock line is high, will be interpreted as control

signals.

Accordingly, the following bus conditions have been defined:

Bus not busy

Both data and clock lines remain high.

Start data transfer

A change in the state of the data line, from high to low, while the clock is high, defines the

START condition.

Stop data transfer

A change in the state of the data line, from low to high, while the clock is high, defines the

STOP condition.

Doc ID 9074 Rev 5

7/27

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