CDP68HC68S1 데이터 시트보기 (PDF) - Intersil

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CDP68HC68S1

Serial Multiplexed Bus Interface

Intersil 

CDP68HC68S1

The Serial Bus IC offers the user three possible modes of

operation as defined by Table 1 - SCl (Note 1), SPl, and Buff-

ered SPl. Also included is a “three-state mode” entered by

pulling the CS pin high while in the Buffered SPI mode. As

the name implies, the SCl mode is used when communicat-

ing through the microcomputer’s SCl port. In this mode,

asynchronous NRZ data format (1 start bit, 8 data bits ‘least

significant bit first’, and 1 stop bit) and baud rate remain the

same on each “side” of the SBlC, i.e. to and from the micro

and to and from the differential network bus.

TABLE 1. MODE AND CHIP SELECT DEFINITION

SBI CHIP MODE

MODE PIN

CS PIN

SCI

1

1

SPI

1

0

Buffered SPI

0

0

Three-State (Note 2)

0

1

NOTES:

1. SCI is the UART interface of a 68HCO5 MCU. The

CDP68HC68S1 is compatable with most UART devices.

2. The three-state mode is only entered when using the Buffered

SPI mode. In the three-state mode, only the XMIT, REC, and

SCK pins are three-stated. The CONTROL and IDLE pins are al-

ways active.

During data transmission, while a byte is being transmitted

from the MCU through the SBl chip onto the differential bus,

it is also reflected and simultaneously received back at the

micro, (this is required for bus arbitration as described later).

DIFFERENTIAL BUS

SBI

SBI

SBI

bus “monitoring”. The Serial BUS Interface chip handles bus

arbitration, data collision detection, and provides short circuit

protection.

A 68HC0S MCU’s SPI port may instead be used for bus

communication. Two modes of SPl operation are available

with the SBIC - one essentially places the 68HC05 micro-

computer in the slave mode and the other allows the MCU to

remain a master. In the normal SPl mode the SBIC acts as a

master and supplies a data-synchronizing serial clock signal

to the micro (which operates in the slave mode) for shifting

data in or out of the micro’s 8-bit SPl data register. Again,

baud rates are the same on each side of the SBlC, however,

the user must reverse the bit order of a byte transmitted or

received via the SPI port due to the SPl’s most significant bit

first serial data nature. In addition, since the user microcom-

puter is operating in the slave mode it must signal the SBI

chip (by pulling the CONTROL line low) to initiate a transmis-

sion. As in the SCl mode, during a transmission, the byte

originally in the SPI data register is replaced by the byte

reflected from the bus.

Transmission and reception of data in the Buffered SPI mode

allows the user to free the micro’s SPl port by allowing fast

data communication (1M bits/second) between the SPI port

and SBlC. For instance, if the MCU is transmitting, the SBlC

converts the data stream from the MCU’s SPl port to a

slower speed for transmission along the differential bus

when the bus becomes idle. Data speed conversion is

accomplished via a 2 byte (16-bit) data buffer register resid-

ing in the serial bus chip. In this mode the MCU operates as

a master and provides the serial clock signal to the slave

SBlC peripheral. After fast data has been sent to or received

from the SBIC, the micro can pull the SBlC’s CS pin high

(placing the SBlC chip in the three-state mode) and then use

the SPl port to access other SPl peripherals.

All transfers between the user MCU and the SBlC in the

Buffered SPI mode consist of 2 bytes, i.e. a message con-

sists an even number of 8-bit transfers. A microcomputer

wishing to transmit loads 2 bytes into the serial bus IC data

register and then pulls the control pin low to initiate transmis-

sion. During transmission the 2 bytes placed into the buffer

are replaced by the two reflected bytes received from the

bus. After every 2 byte transmission the user micro should

transfer the two reflected bytes out of the buffer and the next

2 bytes to be transmitted into the buffer.

TABLE 2. CLOCK PROGRAMMING

SPI OR SCI

MCU

SPI OR SCI

MCU

SPI OR SCI

MCU

FIGURE 1. POSSIBLE NETWORK CONFIGURATION-VARIOUS

MICROCOMPUTERS USING SBI CHIPS TO COM-

MUNICATE ALONG DIFFERENTIAL BUS.

In addition to performing a framing error check in the SCI

mode, other advantages gained by using the SBlC (in any

mode) include greater system EMl tolerance and automatic

CLOCK INPUT

DIVIDE FACTOR

÷1

÷2

÷4

÷ 10

A PIN

0

0

1

1

B PIN

0

1

0

1

6-87

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