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CDP68HC68S1

Serial Multiplexed Bus Interface

Intersil 

CDP68HC68S1

Receive data is an output from the differential transceiver

cell. It is the output of a differential amplifier which decodes

the bus “+” and “-” I/O. When the bus “+” and “-” has been

driven positive and negative respectively to a differential volt-

age value greater than VIDH, the output of the differential

amplifier is a logic one, which is inverted and considered a 0-

bit from the bus. Otherwise, for level below VIDL the differen-

tial amplifier output is a logic zero, which, in turn, is inverted

and considered a 1-bit from the bus.

Twisted wire pair (or adjacent PC board traces) is rec-

ommended for the two differential bus lines.

The BREAK input, when held at a logic zero, (low) causes

the differential transmitter driver to generate a continuous

logic level zero on the differential bus. This action can gener-

ate a data collision which can be either used as a break or a

request for arbitration by the system. When held at logic one,

(high) this input has no effect on the operation of the cell.

The out of range output is normally a logic zero but goes to a

logic one when the common mode voltage on both differen-

tial bus inputs exceeds a voltage value greater than VMAX or

less than VMIN (see device specifications). This output is

used by a latch to hold the received data at the logic level it

was before the over range signal occurred.

Provided on chip is a power-on reset function. The transceiver

cell’s reset output is held to a logic zero on power up and

switches to a logic one at or before VDD rises to 4.0V. This out-

put is used to ensure that other on-board logic has been prop-

erly initiated. During this reset time, the bus “+” and the bus “-”

l/Os provide a high impedance state to the bus.

Bus Speed

SBlC systems typically use a bus speed of 7812.5 bits/sec-

ond which is accomplished by using a 1MHz internal clock.

However, no restriction on any other baud rate is designed

into the chip, except its upper speed limit (see device specifi-

cations).

Bus Byte Format

All bytes transmitted on the bus follow the standard UART

style asynchronous non-return-to zero data format consist-

ing oft start bit (logical zero) followed by 8 data bits (LSB

first), and 1 stop bit (logical one).

Bus Message Format

All messages transmitted on the bus consist of a number of

bytes, from 1 to N, with no restriction on length. The user must

be aware, however, that the longer the message length, the

greater the probability of collision with messages being trans-

mitted at random from other masters on the bus. Typical mes-

sage lengths of systems now in use range from 1 to 4 bytes.

The actual definition of each byte sent is left for the user to

determine, i.e. the user must define the system protocol. For

instance, a typical (and recommended) protocol might dic-

tate that the first byte of each message sent be a unique

address/identification byte. The first byte sent by a node (an

MCU coupled with an SBl chip) might contain address infor-

mation telling where (to which node[s]) the message is tar-

geted for or where the message came from.

Other possibilities would be to identify the type of message

sent (e.g. an instruction or just information) or the length of

the message. The remaining bytes in each message can be

merely data bytes that comprise the actual message. The

user can even use the last byte as a check sum so that all

receiving nodes can check for errors in transmission.

Messages are normally received by all nodes on the bus and

may be processed by one or more micros, i.e., each MCU

may decide, after receiving the first byte (address/ID byte)

that this particular message is not needed for its operation.

The MCU can then ignore the remainder of the message.

Prioritization

Since simultaneous transmission of address/ID bytes from

several microcomputers is a possibility, a system of prioriti-

zation should be determined for bus arbitration. Due to the

electrical characteristics of the differential data bus, each

unique address/ID byte can automatically contain priority

information used for bus arbitration. Merely use “lower” value

ID bytes for higher priority messages. “Lower” value, in the

SBlC case, means an ID byte with more zero’s in its least

significant locations. To further explain, since the differential

bus transmits data least significant bit first and a zero over-

rides a 1-bit simultaneously transmitted by different nodes,

an ID byte with least significant bit equal to zero will override

an ID byte from a micro whose least significant bit is a one. If

this does occur on-chip bus arbitration will automatically

allow only one SBlC chip (with the highest priority address/

ID byte) to continue transmitting. In this case it is the micro

who transmitted the 0-bit. Assuming both ID bytes contain

identical LSBs (bit 0) then arbitration is carried on to the next

bit (bit 1),and soon.

Reflected Data

Whenever a microcomputer sends data through the SBIC

and onto the differential bus, it will always receive reflected

data back. The reflected data is the data that was actually

seen on the bus. Keep in mind that during data collisions

between simultaneously transmitting micros, zeroes override

ones. In addition, any noise that may have been induced on

the bus may alter the resultant reflected byte.

Bus Arbitration

Bus arbitration is the attempted transmission onto the differ-

ential bus of an initial byte (preferably an address/ID byte) by

one or more user microcomputers. The purpose of bus arbi-

tration is to enable a single microcomputer to obtain sole

usage of the bus for the purpose of transmitting a message.

Bus arbitration is accomplished via a combination of meth-

ods which include an MCU software comparison of transmit-

ted bytes to reflected bytes, the SBlC’s collision detection

circuit, and its start bit arbitration detector circuits.

Collision Detection

The SBlC’s collision detector circuit compares the bits being

sent from a user microcomputer to the reflected byte simul-

taneously received back from the differential bus. If the colli-

sion detector detects a difference in the data, it immediately

blocks the user microcomputer’s transmitted data from fur-

6-90

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