MC12202DT 데이터 시트보기 (PDF) - Motorola => Freescale
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MC12202DT Datasheet PDF : 12 Pages
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MC12202
PROGRAMMABLE DIVIDER
19–bit serial data format for the programmable divider is shown below. If the control bit is LOW, data is transferred from the 18–bit
shift register into the 18–bit latch which specifies the swallow A–counter divide ratio (0 to 127) and the programmable N–counter
divide ratio (16 to 2047). An N–counter divide ratio less than 16 is prohibited.
For Control bit (C) = LOW:
MSB (FIRST BIT)
CONTROL BIT (LAST BIT)
LSB
NNNNNNNNNNNAAAAAAAC
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
SETTING BITS FOR
DIVIDE RATIO OF
PROGRAMMABLE N–COUNTER
SETTING BITS FOR
DIVIDE RATIO OF
SWALLOW A–COUNTER
DIVIDE RATIO OF PROGRAMMABLE N–COUNTER
DIVIDE RATIO OF SWALLOW A–COUNTER
Divide N N N N N N N N N N N Divide A A A A A A A
Ratio N 18 17 16 15 14 13 12 11 10 9 8 Ratio A 7 6 5 4 3 2 1
16
00000010000
0
0000000
17
00000010001
1
0000001
•
•••••••••••
•
•••••••
2047 1 1 1 1 1 1 1 1 1 1 1
127
111
1111
DIVIDE RATIO SETTING
fvco = [(P•N)+A]•fosc ÷ R with A<N
fvco: Output frequency of external voltage controlled oscillator (VCO)
N: Preset divide ratio of binary 11–bit programmable counter (16 to 2047)
A: Preset divide ratio of binary 7–bit swallow counter (0 to 127, A<N)
fosc: Output frequency of the external frequency oscillator
R: Preset divide ratio of binary 14–bit programmable reference counter (8 to 16383)
P: Preset mode of dual modulus prescaler (64 or 128)
DATA
CLK
N18:MSB
(SW:MSB)
N17
(R14)
N8 A7
(R7) (R6)
A1 C = CONTROL BIT (LAST BIT)
(R1) (C = CONTROL BIT (LAST BIT))
LE
ts(C→LE)
ts(D)
th(D)
tCW
NOTES:Programmable reference divider data shown in parenthesis. Data shifted into register on rising edge of CLK.
ts(D) = Setup Time DATA to CLK
th(D) = Hold Time DATA to CLK
tCW = CLK Pulse Width
tEW = LE Pulse Width
ts(C→LE) = Setup Time CLK to LE
ts(D) ≥ 10ns
th(D) ≥ 20ns
tCW ≥ 30ns
tEW ≥ 20ns
ts(C→LE) ≥ 30ns
Figure 2. Serial Data Input Timing
HIPERCOMM
5
BR1334 — Rev 4
tEW
MOTOROLA
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