MT28F320J3RG-15ETF 데이터 시트보기 (PDF) - Micron Technology

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MT28F320J3RG-15ETF

Q-FLASH™ MEMORY

Micron Technology 

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

PIN/BALL DESCRIPTIONS

56-PIN TSOP 64-BALL FBGA

NUMBERS

NUMBERS SYMBOL TYPE

DESCRIPTION

55

G8

WE# Input Write Enable: Determines if a given cycle is a WRITE

cycle. If WE# is LOW, the cycle is either a WRITE to the

command execution logic (CEL) or to the memory array.

Addresses and data are latched on the rising edge of the

WE# pulse.

14, 2, 29

B4, B8, H1

CE0, CE1, Input

CE2

Chip Enable: Three CE pins enable the use of multiple

Flash devices in the system without requiring additional

logic. The device can be configured to use a single CE

signal by tying CE1 and CE2 to ground and then using

CE0 as CE. Device selection occurs with the first edge of

CE0, CE1, or CE2 (CEx) that enables the device. Device

deselection occurs with the first edge of CEx that

disables the device (see Table 2).

16

D4

RP# Input Reset/Power-Down: When LOW, RP# clears the status

register, sets the ISM to the array read mode, and places

the device in deep power-down mode. All inputs,

including CEx, are “Don’t Care,” and all outputs are

High-Z. RP# must be held at VIH during all other modes

of operation.

54

F8

OE# Input Output Enables: Enables data ouput buffers when LOW.

When OE# is HIGH, the output buffers are disabled.

32, 28, 27,

26, 25, 24, 23,

22, 20, 19, 18,

17, 13, 12, 11,

10, 8, 7, 6, 5, 4,

3, 1, 30

G2, A1, B1, C1,

D1, D2, A2, C2,

A3, B3, C3, D3,

C4, A5, B5, C5,

D7, D8, A7, B7,

C7, C8, A8, G1

A0–A21/

(A22)

(A23)

Input

Address inputs during READ and WRITE operations. A0 is

only used in x8 mode. A22 (pin 1, ball A8) is only

available on the 64Mb and 128Mb devices. A23 (pin 30,

ball G1) is only available on the 128Mb device.

31

F1

BYTE# Input BYTE# LOW places the device in the x8 mode. BYTE#

HIGH places the device in the x16 mode and turns off

the A0 input buffer. Address A1 becomes the lowest

order address in x16 mode.

15

A4

VPEN Input Necessary voltage for erasing blocks, programming data,

or configuring lock bits. Typically, VPEN is connected to

VCC. When VPEN ≤ VPENLK, this pin enables hardware write

protect.

33, 35, 38, 40,

44, 46, 49, 51,

34, 36, 39, 41,

45, 47, 50, 52

F2, E2, G3, E4,

E5, G5, G6, H7,

E1, E3, F3, F4,

F5, H5, G7, E7

DQ0– Input/ Data I/O: Data output pins during any READ operation

DQ15 Output or data input pins during a WRITE. DQ8–DQ15 are not

used in byte mode.

53

E8

STS Output Status: Indicates the status of the ISM. When configured

in level mode, default mode it acts as an RY/BY# pin.

When configured in its pulse mode, it can pulse to

indicate program and/or erase completion. Tie STS to

VCCQ through a pull-up resistor.

(continued on next page)

128Mb, 64Mb, 32Mb Q-Flash Memory

MT28F640J3_7.p65 – Rev. 6, Pub. 8/02

6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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