MT28F320J3RG-11ET 데이터 시트보기 (PDF) - Micron Technology
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MT28F320J3RG-11ET Datasheet PDF : 52 Pages
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128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
MEMORY ARCHITECTURE
The MT28F128J3, MT28F640J3, and MT28F320J3
memory array architecture is divided into one hun-
dred twenty-eight, sixty-four, or thirty-two 128KB
blocks, respectively (see Figure 1). The internal archi-
tecture allows greater flexibility when updating data
because individual code portions can be updated in-
dependently of the rest of the code.
Figure 1
Memory Map
FFFFFFh
FE0000h
128KB Block
7FFFFFh
127
7F0000h 64K-Word Block 127
Table 2
Chip Enable Truth Table
CE2
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
CE1
VIL
VIL
VIH
VIH
VIL
VIL
VIH
VIH
CE0
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
DEVICE
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
7FFFFFh
7E0000h
128KB Block
63
3FFFFFh
3F0000h
64K-Word Block 63
3FFFFFh
3E0000h
128KB Block
31
1FFFFFh
1F0000h
64K-Word Block 31
03FFFFh
020000h
01FFFFh
000000h
128KB Block
1
128KB Block
0
A0–A23: 128Mb
A0–A22: 64Mb
A0–A21: 32Mb
Byte-Wide (x8) Mode
01FFFFh
010000h
00FFFFh
000000h
64K-Word Block 1
64K-Word Block 0
A1–A23: 128Mb
A1–A22: 64Mb
A1–A21: 32Mb
Word-Wide (x16) Mode
BUS OPERATION
All bus cycles to and from the Flash memory must
conform to the standard microprocessor bus cycles.
The local CPU reads and writes Flash memory in-
system.
READ
Information can be read from any block, query, iden-
tifier codes, or status register, regardless of the VPEN
voltage. The device automatically resets to read array
mode upon initial device power-up or after exit from
reset/power-down mode. To access other read mode
commands (READ ARRAY, READ QUERY, READ IDEN-
TIFIER CODES, or READ STATUS REGISTER), these
commands should be issued to the CUI. Six control
pins dictate the data flow in and out of the device: CE0,
CE1, CE2, OE#, WE#, and RP#. In system designs using
multiple Q-Flash devices, CE0, CE1, and CE2 (CEx)
select the memory device (see Table 2). To drive data
out of the device and onto the I/O bus, OE# must be
active and WE# must be inactive (VIH).
When reading information in read array mode, the
device defaults to asynchronous page mode, thus pro-
viding a high data transfer rate for memory subsystems.
In this state, data is internally read and stored in a
NOTE: For single-chip applications, CE2 and CE1 can be
connected to GND.
high-speed page buffer. A0–A2 select data in the page
buffer. Asynchronous page mode, with a page size of
four words or eight bytes, is supported with no addi-
tional commands required.
OUTPUT DISABLE
The device outputs are disabled with OE# at a logic
HIGH level (VIH). Output pins DQ0–DQ15 are placed in
High-Z.
STANDBY
CE0, CE1, and CE2 can disable the device (see
Table 2) and place it in standby mode, which substan-
tially reduces device power consumption. DQ0–DQ15
outputs are placed in High-Z, independent of OE#. If
deselected during block erase, program, or lock bit con-
figuration, the ISM continues functioning and consum-
ing active power until the operation completes.
RESET/POWER-DOWN
RP# puts the device into the reset/power-down
mode when set to VIL.
During read, RP# LOW deselects the memory, places
output drivers in High-Z, and turns off internal cir-
cuitry. RP# must be held LOW for a minimum of tPLPH.
tRWH is required after return from reset mode until
initial memory access outputs are valid. After this wake-
up interval, normal operation is restored. The com-
mand execution logic (CEL) is reset to the read array
mode and the status register is set to 80h.
During block erase, program, or lock bit configura-
tion, RP# LOW aborts the operation. In default mode,
STS transitions LOW and remains LOW for a maximum
time of tPLPH + tPHRH, until the RESET operation is
complete. Any memory content changes are no longer
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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