MT28F320J3RG-11F 데이터 시트보기 (PDF) - Micron Technology

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MT28F320J3RG-11F

Q-FLASH™ MEMORY

Micron Technology 

valid; the data may be partially corrupted after a pro-

gram or partially changed after an erase or lock bit

configuration. After RP# goes to logic HIGH (VIH), and

after tRS, another command can be written.

It is important to assert RP# during system reset.

After coming out of reset, the system expects to read

from the Flash memory. During block erase, program,

or lock bit configuration mode, automated Flash memo-

ries provide status information when accessed. When

a CPU reset occurs with no Flash memory reset, proper

initialization may not occur because the Flash memory

may be providing status information instead of array

data. Micron Flash memories allow proper initializa-

tion following a system reset through the use of the RP#

input. RP# should be controlled by the same RESET#

signal that resets the system CPU.

READ QUERY

The READ QUERY operation produces block status

information, CFI ID string, system interface informa-

tion, device geometry information, and extended query

information.

READ IDENTIFIER CODES

The READ IDENTIFIER CODES operation produces

the manufacturer code, device code, and the block lock

configuration codes for each block (see Figure 2). The

block lock configuration codes identify locked and un-

locked blocks.

WRITE

Writing commands to the CEL allows reading of de-

vice data, query, identifier codes, and reading and clear-

ing of the status register. In addition, when VPEN = VPENH,

block erasure, program, and lock bit configuration can

also be performed.

The BLOCK ERASE command requires suitable com-

mand data and an address within the block. The BYTE/

WORD PROGRAM command requires the command

and address of the location to be written to. The CLEAR

BLOCK LOCK BITS command requires the command

and any address within the device. SET BLOCK LOCK

BITS command requires the command and the block to

be locked. The CEL does not occupy an addressable

memory location. It is written to when the device is

enabled and WE# is LOW. The address and data needed

to execute a command are latched on the rising edge of

WE# or the first edge of CEx that disables the device

(see Table 2). Standard microprocessor write timings

are used.

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Figure 2

Device Identifier Code Memory Map

7FFFFFh

Block 127

Reserved for Future

Implementation

7F0003h

7F0002h

7F0000h

7EFFFFh

Block 127 Lock Configuration

Reserved for Future

Implementation

(Blocks 64 through 126)

3FFFFFh

Block 63

3F0003h

3F0002h

Reserved for Future

Implementation

Block 63 Lock Configuration

3F0000h

3EFFFFh

Reserved for Future

Implementation

(Blocks 32 through 62)

Block 31

Reserved for Future

Implementation

1F0003h

1F0002h Block 31 Lock Configuration

1F0000h

1EFFFFh

Reserved for Future

Implementation

(Blocks 2 through 30)

01FFFFh

Block 1

010003h

Reserved for Future

Implementation

010002h Block 1 Lock Configuration

010000h

00FFFFh

000004h

Reserved for Future

Implementation

Block 0

Reserved for Future

Implementation

000003h

000002h

000001h

000000h

Block 0 Lock Configuration

Device Code

Manufacturer Code

NOTE: When obtaining these identifier codes, A0 is not used

in either x8 or x16 modes. Data is always given on the

LOW byte in x16 mode (upper byte contains 00h).

128Mb, 64Mb, 32Mb Q-Flash Memory

MT28F640J3_7.p65 – Rev. 6, Pub. 8/02

9

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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