LC587006 데이터 시트보기 (PDF) - SANYO -> Panasonic

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LC587006

Single-Chip 4-Bit Microprocessors with LCD Driver, 2 Kb RAM, and 8, 12, or 16 KB ROM on chip

SANYO -> Panasonic 

LC587008, 587006, 587004

Continued from preceding page.

Pin

SO1

SO2

SO3

SO4

N1

N2

N3

N4

INT

RES

TST

Seg1,

Seg2 to

Seg35

QIP-80

I/O

Pin No.

Function

Option

At reset

I/O ports

• Transistors to hold

Function: The same as for pins A1 to A4

a low or high level

Pins SO1 to SO3 area also used for the serial interface.

7

• Use of these pins in serial mode can be selected under program

I/O

8

control.

9

• Pin functions: SO1: Serial input pin

10

SO2: Serial output pin

• Selection of either

pull-up or pull-

down resistors

• Internal serial clock

divisor selection

The same as for K1

to K4

SO3: Serial clock pin

I 1/1

The serial clock pin can be switched between internal and external,

II 1/2

and between rising edge output and falling edge output.

III 1/4

Output

Input

Input

Input

Output

39

40

41

42

6

5

43

44,

45 to

78

Output-only ports

• Output pins used to output data from RAM

• An alarm signal can be output from pin N4. (Note that this is only

when the N4 output latch is low.)

• An alarm signal modulated at 1, 2 or 4 kHz can be output. (These

frequencies are output when ø0 is 32.768 kHz.)

• A carrier signal can be output from N3. (Note that this is only when

the N3 output latch is low.)

Input ports

• External interrupt request inputs

• Input pins used to read data into RAM

• Input detection can be performed on either rising or falling edges.

• Built-in pull-up/pull-down resistors

LSI internal reset input

• The reset input level can be selected to be either high or low.

• Built-in pull-up/pull-down resistors

• Note: The reset pulse must be at least 500 µs.

Test input

• QIP80 products: Connect to VSS.

• Chip products: Leave open or connect to VSS.

• LCD panel drive/general-purpose output

— LCD panel drive

I STATIC

II 1/2 bias – 1/2 duty

III 1/2 bias – 1/3 duty

IV 1/2 bias – 1/4 duty

V 1/3 bias – 1/3 duty

VI 1/3 bias – 1/4 duty

Types I to V can be specified as mask options.

— General-purpose output mode

I CMOS

II P-channel open drain

III N-channel open drain

Types I to III can be specified as mask options.

• LCD/general-purpose output control is handled by the segment PLA,

and thus program control is not required.

• These pins support output latch control on reset and in standby

states when the oscillators are stopped.

• Arbitrary combinations of LCD drive and general-purpose outputs can

be used.

• Pins N1 to N4

output circuit type:

I CMOS

II N-channel

open drain

• Pins N1 to N4

output level

I High level

II Low level

The output levels on

pins N1 to N4 can be

specified as an option.

• Transistors to hold

a low or high level

• Selection of either

pull-up or pull-

down resistors

• Signal conversion

(rising/falling)

selection

* Only when the

input resistor open

specification is

selected

• LCD driver/

general-purpose

output switching

• LCD drive type

switching

— STATIC

— 1/2 bias – 1/2

duty

— 1/2 bias – 1/3

duty

— 1/2 bias – 1/4

duty

— 1/3 bias – 1/3

duty

— 1/3 bias – 1/4

duty

• General-purpose

output circuit

switching

— CMOS

— P-channel

open drain

— N-channel

open drain

• Output latch control

in standby modes

• LCD drive

— All segments on

— All segments off

*: Determined by

mask options

• General purpose

outputs

— High level

— Low level

*: Determined by

mask options

Note: When a

combination of

LCD drive and

general-

purpose

outputs, the

output state is

either:

— All lit/high level

— All off/low level.

• These pins go to

the static drive

mode during the

reset period.

Continued on next page.

No. 4435-6/29

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