LTC1292(RevB) 데이터 시트보기 (PDF) - Linear Technology

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LTC1292
(Rev.:RevB)

Single Chip 12-Bit Data Acquisition Systems

Linear Technology 

BLOCK DIAGRA

8

VCC

INPUT

SHIFT

REGISTER

+IN

–IN

2

3

ANALOG

INPUT MUX

4

GND

SAMPLE

AND

HOLD

COMP

12-BIT

CAPACITIVE

DAC

5

VREF

LTC1292/LTC1297

7

CLK

OUTPUT

SHIFT

REGISTER

6

DOUT

12-BIT

SAR

CONTROL

AND

TIMING

1

CS

LTC1292/7 BD

TEST CIRCUITS

On and Off Channel Leakage Current

5V

ION

A

ON CHANNEL

IOFF

A

OFF CHANNEL

POLARITY

Load Circuit for tdis and ten

TEST POINT

LTC1292/7 TC01

DOUT

3k

100pF

5V tdis WAVEFORM 2, ten

tdis WAVEFORM 1

LTC1292/7 TC02

Load Circuit for tdDO, tr and tf

1.4V

DOUT

3kΩ

100pF

TEST POINT

LTC1292/7 TC03

Voltage Waveforms for DOUT Delay Time, tdDO

CLK

DOUT

0.8V

tdDO

2.4V

0.4V

LTC1292/7 TC04

Voltage Waveforms for DOUT Rise and Fall Times, tr, tf

2.4V

DOUT

0.4V

tr

tf

LTC1292/7 TC05

Voltage Waveforms for tdis

CS

2.0V

DOUT

WAVEFORM 1

(SEE NOTE 1)

DOUT

WAVEFORM 2

(SEE NOTE 2)

90%

tdis

10%

LTC1292/7 TC06

NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.

NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.

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