LTC1292 데이터 시트보기 (PDF) - Linear Technology

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LTC1292

Single Chip 12-Bit Data Acquisition Systems

Linear Technology 

LTC1292/LTC1297

APPLICATI S I FOR ATIO

ANALOG

INPUTS

LTC1292

CS

CLK

DOUT

MC68HC11

DO

SCK

MISO

DOUT FROM LTC1292 STORED ON MC68HC11 RAM

MSB

LOCATION #61 O O O O B11 B10 B9 B8 BYTE 1

LOCATION #62

B7 B6 B5 B4 B3

B2 B1 B0 BYTE 2

LTC1292/7 F02

Figure 2. Hardware and Software Interface to Motorola MC68HC11 Microcontroller

MC68HC11 CODE for LTC1292 Interface

LABEL MNEMONIC

LDAA

STAA

LDAA

STAA

LDAA

OPERAND

#$50

$1028

#$1B

$1009

#$00

STAA

LOOP LDX

$50

#$1000

LDAB

#$00

LDAA

$50

STAA

$102A

NOP

COMMENTS

CONFIGURATION DATA FOR SPCR

LOAD DATA INTO SPCR ($1028)

CONFIG. DATA FOR PORT D DDR

LOAD DATA INTO PORT D DDR

LOAD DUMMY DIN WORD INTO

ACC A

LOAD DUMMY DIN DATA INTO $50

LOAD INDEX REGISTER X WITH

$1000

LOAD ACC B WITH $00

LOAD DUMMY DIN INTO ACC A

FROM $50

LOAD DUMMY DIN INTO SPI,

START SCK

DELAY CS FALL TIME TO RIGHT

JUSTIFY DATA

LABEL MNEMONIC OPERAND

STAB

$08, X

NOP

LDAA

LDAA

STAA

STAA

$1029

$102A

$61

$102A

NOPS

BSET

LDAA

LDAA

STAA

JMP

$08,X,$01

$1029

$102A

$62

LOOP

COMMENTS

D0 GOES LOW (CS GOES LOW)

6 NOPS FOR TIMING

CHECK SPI STATUS REG

LOAD LTC1292 MSBs INTO ACC A

STORE MSBs IN $61

LOAD DUMMY DIN INTO SPI,

START SCK

6 NOPS FOR TIMING

D0 GOES HIGH (CS GOES HIGH)

CHECK SPI STATUS REGISTER

LOAD LTC1292 LSBs IN ACC

STORE LSBs IN $62

START NEXT CONVERSION

the MPU. The data is right-justified in the two memory

locations (Figure 2). This was made possible by delaying

the falling edge of CS till after the second CLK. ANDing the

first byte with 0FHEX clears the four most significant bits.

This operation was not included in the code. It can be

inserted in the data gathering loop or outside the loop

when the data is processed.

For the LTC1297 (Figure 3) a delay must be introduced to

accommodate the setup time, tsuCS, before the dummy

DIN word is sent to the data register. The first 8-bit transfer

clocks B11 through B6 of the A/D conversion result into

the processor. The second 8-bit transfer clocks the re-

maining bits B5 through B0 into the MPU. Note B1 and B2

from the LSB-first data word have also been clocked in.

CS

CLK

DOUT

MPU

RECEIVED WORD

?

B11 B10 B9 B8 B7 B6

BYTE 1

0 B11 B10 B9 B8 B7 B6

1ST TRANSFER

B5

B4 B3 B2 B1 B0 B1 B2

B3

BYTE 2

B5 B4 B3 B2 B1 B0 B1 B2

2ND TRANSFER

Figure 3. Data Exchange Between LTC1297 and MC68HC11

10

LTC1292/7 F03

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