VES9600 데이터 시트보기 (PDF) - Philips Electronics

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VES9600

Single Chip DVB-T Channel Receiver

Philips Electronics 

Philips Semiconductors

Single Chip DVB-T Channel Receiver

Product specification

VES9600

SP_IN[3:0]

SP_OUT[7:0]

CTRL[1:0]

DS_SPARE_1

72-73-74-75

88-89-90-91-92-

93-94-95

84-85

28

(3.3)

I

O

(3.3)

O

(3.3)

O

(5V)

DS_SPARE_2

29

O

(5V)

TESTADC

55

I

Spare inputs

Spare outputs

control detection signal, flag monitoring outputs.

Spare delta-sigma output. Managed by the DSP to handle a low

frequency DAC. ( automatic first stage tuner AGC measurement for

example).

Spare delta-sigma output. Managed by the DSP or by an I2C register

to generate an analog level. (after a RC low-pass filter)

Must be set to “1”

TCK

TDI

TMS

TRST

TDO

BOUNDARY SCAN

187

I

clock signal for boundary-scan. Wired to GND (if not used)

188

I

Input port for boundary-scan. Wired to GND (if not used)

190

I

Mode programming signal for boundary-scan. Wired to GND (if not

used)

189

I Asynchronous reset signal for boundary-scan. Wired to GND (if not

used)

191

O

(5V)

Output port for boundary-scan. NC (if not used)

GND

VCC

VDD

2-10-18-31-69- GN

71-80-87-97-

117-123-134-

142-149-165-

177-183-193-201

1-30-68-79-192 VCC

5V

7-17-70-86-96- VDD

116-122-133- 3.3V

141-148-164-

176-182-200

POWER SUPPLIES

Ground level 0 V

Positive Power Supply 5 V typical

Positive Power Supply 3.3 V typical

FIGURE 2 : BLOCK DIAGRAM

FI[9:0] 10

CLR#

VIP

VIM

VDD GND VCC VDi VSi

44

RECOV_DATA

24

XIN XOUT POWER SUPPLIES

MONITORING

SACLK

VAGC

SDA_TUN

SCL_TUN

INPUTS

VES9600

OUTPUTS

IT

FEL

PSYNC

UNCOR

DEN

INTERFACE

DSP_INTERFACE

JTAG

OCLK

8

DO[7:0]

1999 Sep 01

3

SADDR[1:0] SCL SDA

3

SDA_EEP SDI_TDO

7

4

TDO

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