XRT71D00 데이터 시트보기 (PDF) - Exar Corporation

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XRT71D00

E3/DS3/STS-1 JITTER ATTENUATOR

Exar Corporation 

XRT71D00

E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

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PIN DESCRIPTIONS

PIN DESCRIPTION

PIN #

1

2

3

NAME

NC

RNEG

RClk

TYPE

DESCRIPTION

*** This pin is not connected internally

I Receive Negative Data (Jittery) Input

The input jittery negative data is sampled either on the rising or falling edge of RClk

depending on the setting of ClkES (pin 10). This data will ultimately be output via the

RRNEG output pin.

If ClkES is “high”, then RNEG will be sampled on the falling edge of RClk.

If ClkES is “low”, then RPOS will be sampled on the rising edge of RClk.

This pin is typically tied to the “RNEG” output pin of the LIU.

NOTES:

1. For “Jitter Attenuator” applications, this pin is typically connected to the

“RNEG” output pin of the corresponding LIU IC.

2. The user should tie this input pin to “GND” for “SONET De-Synchronization”

and “Single-Rail Jitter Attenuator” Applications.

I Receive Clock (Jittery) Input

The user is expected to supply the “jittery” clock signal (e.g., the clock signal that needs

to be “smoothed”) to this input pin.

For Jitter Attenuation Applications:

The user should connect the “Recovered Line Clock” (RCLK) output signal (of the DS3,

E3 or STS-1 LIU IC) to this input pin.

For SONET De-synchronizer Applications:

The user should connect the “Receive DS3 Output” clock signal (of the OC-N to DS3

Mapper/De-Mapper IC) to this input pin.

The XRT71D00 device will use this clock signal to latch the data, residing on the

“RPOS” and “RNEG” input pins, into the chip.

If the “CLKES” input pin (or bit-field) is “high”, then the XRT71D00 device will sample

the data on the “RPOS” and “RNEG” input pins, on the falling edge of the “RCLK” clock

signal.

If the “CLKES” input pin (or bit-field) is “low”, then the XRT71D00 device will sample the

data on the “RPOS” and “RNEG” input pins, on the rising edge of the “RCLK” clock sig-

nal.

4

GND

*** Digital Ground

5

MClk

I Master Clock Input.

This input pin functions as the reference clock for the internal PLL. The user is

expected to apply a 44.736MHz+/-20ppm (for DS3 applications), 34.368MHz+/-

20ppm (for E3 applications) or a 51.84MHz+/- 20ppm (for STS-1 applications) to this

input pin. This clock must be continuous and jitter free with duty cycle between 30 to

70%.

6

GND

*** Analog Ground

7

VDD

*** Analog Positive Supply: 3.3V or 5.0V ± 5%

3

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