PM5945 데이터 시트보기 (PDF) - PMC-Sierra

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PM5945

SONET ATM PHYSICAL INTERFACE BOARD

PMC-Sierra 

S TANDARD PRODUCT

PMC-Sierra, Inc.

PM5945 SAPI

PMC-940106 ISSUE 3, May 16, 1994

SAPI DAUGHTERBOARD

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This allows a diagnostic loopback to be done at the Cypress part which will verify

the connections and functionality between the Cypress device and the SUNI device.

done. Writing a binary xxxxxxx0 to this address will disable transmit diagnostic

loopback. The most significant 7 bits of data are don't cares. This is a write only bit.

A hardware reset removes the transmit loopback enable (if it was set).

INTERFACE DESCRIPTION

UTOPIA Interface

The UTOPIA Interface makes the SUNI drop side receive and transmit signals

compatible with the UTOPIA 1.04 interface specification. It consists of two high

speed 22V10 PALs, two high speed IDT74FCT377C buffers, and a receive

IDT72201 clocked FIFO. The 22V10 PALs can be replaced with faster versions if

you must run at a higher than 20 MHz TxClk and RxClk clock signals.

The Transmit drop side interface is controlled by the ATM layer through the edge

connector. All the transmit signals from the ATM layer change with respect to the

TxClk. All the input signals to the ATM layer are sampled on the rising edge of the

TxClk.

The SUNI device asserts the TCA signal when it has a complete empty cell

available. This signal goes to the PAL (U17) and causes the TxFullB signal to the

ATM layer to be de-asserted (high). The ATM layer asserts the TxClavB signal (low)

when it has a complete Cell of data to transfer to the PHY device. The TxEnbB

signal from the ATM layer (Vicksburg card) is the output of the TxFullB signal from

the PHY layer gated with the TxClavB signal from the ATM layer. The way the

TxEnbB signal goes active (low) depends on whether the ATM layer is ready to send

a cell of data before the PHY layer becomes available to accept the data, or whether

the PHY layer is ready to accept a cell of data before the ATM layer is ready to send

data.

The case where the ATM layer has a cell available for transmission before the PHY

layer is ready to accept the cell is handled as follows; The Vicksburg card drives the

TSOC signal active (high) and the TxData bus with valid octet byte zero coincident

with the assertion of the TxClavB signal, and waits for the TxFullB signal from the

PHY layer to go inactive (high). When the PHY device has a cell available, the

TxFullB signal goes inactive (high) and then the TxEnbB signal is immediately

asserted (low) (after a delay through a gate). On the next rising edge of the TxClk

signal, the second byte of data is driven onto the TxData bus and the TSOC signal is

de-asserted (low).

The case where the PHY layer is ready to accept a cell of data before the ATM layer

is ready to transmit the cell is handled as follows; The PHY layer de-asserts the

TxFullB signal (high) and waits for the TxEnbB signal to go active (low). When the

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