UPD16732AN-XXX 데이터 시트보기 (PDF) - NEC => Renesas Technology
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UPD16732AN-XXX
NEC => Renesas Technology
UPD16732AN-XXX Datasheet PDF : 24 Pages
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µ PD16732A, 16732B
Timing Requirement (TA = –10 to +75 °C, VDD1 = 2.3 V to 3.6 V, VSS1 = VSS2 = 0 V, tr = tf = 8.0 ns)
Parameter
Clock Pulse Width
Clock Pulse High Period
Clock Pulse Low Period
Data Setup Time
Data Hold Time
Start Pulse Setup Time
Start Pulse Hold Time
POL2 Setup Time
POL2 Hold Time
Start Pulse Low Period
STB Pulse Width
Symbol
PWCLK
PWCLK(H)
PWCLK(L)
tSETUP1
tHOLD1
tSETUP2
tHOLD2
tSETUP3
tHOLD3
tSPL
PWSTB
Condition
VDD1 = 2.3 V to 3.6 V
VDD1 = 3.0 V to 3.6 V
VDD1 = 2.3 V to 3.6 V
VDD1 = 3.0 V to 3.6 V
Data Invalid Period
Last Data Timing
CLK-STB Time
STB-CLK Time
Time Between STB and Start Pulse
POL-STB Time
• STB-POL Time
tINV
tLDT
tCLK-STB
tSTB-CLK
tSTB-STH
tPOL-STB
tSTB-POL
CLK ↑ → STB ↑
STB ↑ → CLK ↑
VDD1 = 2.3 V to 3.6 V
STB ↑ → CLK ↑
VDD1 = 3.0 V to 3.6 V
STB ↑ → STHR(STHL) ↑
POL ↑ or ↓ → STB ↑
STB ↓ → POL ↓ or ↑
MIN.
22
15
4
6
4
4
0
4
0
4
0
6
2
1
2
6
9
6
2
–5
6
TYP.
MAX.
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
µs
CLK
CLK
ns
ns
ns
CLK
ns
ns
Data Sheet S13972EJ3V0DS00
17
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