MC145402 데이터 시트보기 (PDF) - Motorola => Freescale
부품명
상세내역
제조사
MC145402 Datasheet PDF : 16 Pages
| |||
PIN DESCRIPTIONS
VDD
Positive Supply (Pin 16)
The most positive power supply, typically + 5 V in split
power supply configurations, or + 10 V in single supply
systems.
VSS
Negative Supply (Pin 8)
The most negative power supply, typically – 5 V in split
power supply configurations, or 0 V in single supply systems.
VAG
Analog Ground (Pin 1)
This is the analog signal reference point. This pin is nor-
mally tied to 0 V in split supply operation or VDD/2 in single
supply systems.
VDG
Digital Ground (Pin 9)
This is the ground reference for all of the digital input and
output pins. CMOS compatible logic signals swing from VDG
to VDD where VDG can be established anywhere from VDD –
4.75 V to VSS.
Aout
Analog Output (Pin 2)
This is the output of the decoder’s sample and hold circuit
and is a 100% duty cycle analog output of the last digital
word received and decoded by the decoder. Aout is updated
approximately 60 ns after the rising edge of the last CCI prior
to MSI (see Figure 2). Aout is capable of driving a 10 kΩ,
50 pF load.
Ain
Analog Input (Pin 3)
This is the high–impedance input to the coder. An A/D
cycle begins on the first falling edge of CCI following the ris-
ing edge of MSI. Ain is sampled approximately 50 ns after the
rising edge of CCI prior to the start of the A/D cycle.
PDI
Power–Down Input (Pin 4)
In normal operation this Input should be tied high. A logic
low on this input puts the device into a minimum power dissi-
pation mode. During power–down, all functions stop. Two
complete MSI conversion cycles are required to establish
normal operation after leaving the power–down mode.
CCI
Convert Clock Input (Pin 5)
This input controls the complete conversion sequence dur-
ing one MSI cycle and must receive a clock which is 32 times
the frequency of MSI. The only exception to 32 times the fre-
quency of MSI is during short–cycle operation. See General
Modes of Operation section. CCI must be synchronous and
approximately rising edge aligned with MSI.
MSI
Master Sync Input (Pin 6)
This pin determines the conversion rate for both the coder
and the decoder. One A/D and D/A conversion takes place
during each period of the digital clock applied to this input
(except in short–cycle operation, see General Modes of
Operation section). MSI must be synchronous and approxi-
mately rising edge aligned with CCI.
TDC
Transmit Data Clock (Pin 12)
Digital data from the coder is serially transmitted from TDD
on rising TDC edges whenever TDE is a logic high. TDC
must be approximately rising edge aligned with TDE. Gener-
ally, if TDC is low when TDE rises, the first rising edge of
TDC clocks the first data bit. If TDC is high when TDE rises,
the first bit will be clocked by TDE and the first rising edge of
TDC after TDE rises will clock out the second data bit.
TDE
Transmit Data Enable (Pin 10)
This pin is used to initiate the serial transfer of data from
the coder and provides three–state control of the TDD pin.
The rising edge of TDE (or TDC if it follows TDE) signals the
start of data transfer from the TDD pin. A resulting high logic
level on TDE also releases TDD from its high–impedance
state. TDE must remain high throughout the data transfer to
keep TDD in the low–impedance state and must return to a
low state prior to each data transfer. If TDE remains high for
more than 16 TDC clocks, the 16 bits of TDD data will be re-
circulated. (Note: The A/D cycle begins on the first falling
edge of CCI after the rising edge of MSI. The internal trans-
mit latch is updated one and one half CCI periods prior to the
start of the A/D cycle. A pulse generated by the logical AND
of TDE and the first TDC transfers data to the transmit shift
register, and this pulse must not occur when the transmit
latch is updated. See Figure 2 and see tsu6, tsu6′, and tsu7
of Figure 1.
TDD
Transmit Digital Data (Pin 11)
This is the three–state output data pin from the coder and
is controlled by the TDE and TDC pins. TDD is in the high–
impedance state whenever TDE is a logic low. The first data
bit is output from TDD on the rising edge of TDE (or TDC if it
follows TDE) and each subsequent bit is output on rising
edges of TDC. Two output data formats are available as de-
scribed in the TDF pin description below.
TDF
Transmit Data Format (Pin 7)
The 13–bit digital output of the coder is available in one of
two 16–bit two’s complement formats as determined by the
state of this pin. A logic 0 at this pin causes the data from
TDD to be in a 16–bit sign–extended format as follows:
SSSSM ... L where S, M, and L represent the sign, most sig-
nificant bit, and the least significant bit, respectively. A logic 1
on this pin formats the data as follows: SM ... LSSS (see Fig-
ure 3). RDD data is not affected by the state of this pin and if
a “digital loopback” is needed (TDD data looped back into
RDD), this pin should be high.
MC145402
6
MOTOROLA
Share Link: 