MC145402 데이터 시트보기 (PDF) - Motorola => Freescale
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MC145402 Datasheet PDF : 16 Pages
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RDC
Receive Data Clock (Pin 13)
Receive digital data is accepted by the decoder on the first
13 falling edges of RDC after an RCE rising edge.
RCE
Receive Clock Enable (Pin 14)
This pin identifies the beginning of a data transfer into the
RDD pin of the decoder. The first 13 falling edges of RDC af-
ter an RCE rising edge will clock data into the decoder data
input, RDD. RCE must return low prior to each data transfer.
Since receive data is latched into the receive latch on the last
CCI falling edge prior to MSI, data transfers may not span
this falling edge of CCI without loss of data.
RDD
Receive Digital Data (Pin 15)
This pin is the data input to the decoder and is controlled
by the RDC and RCE pins described above. Two’s comple-
ment data are loaded in the following sequence: SM ... L
where S, M, and L represent the sign, most significant bit,
and the least significant bit, respectively. Only the first 13 bits
clocked by RDC after RCE rises will be accepted for decod-
ing. Any additional bits will be ignored (see Figure 3).
GENERAL INFORMATION
GENERAL MODES OF OPERATION
The MC145402 has three modes of operation; a “full” cycle
mode and two ‘‘short” cycle modes. The full cycle mode al-
lows simultaneous analog–to–digital (A/D) and digital–to–
analog (D/A) operation. The short cycle modes allow either
A/D only or D/A only operation. Two MSI cycles are required
for the MC145402 to detect which operating mode has been
selected. See Figure 2 for full versus short cycle clocking.
Full Cycle Operation
When operating in the full cycle mode, the MC145402 per-
forms a 13–bit A/D conversion followed by a 13–bit D/A con–
version. Full cycle operation is selected by using a CCI
frequency that is 32 times the frequency of MSI. MSI is the
sample rate frequency.
Short Cycle Analog–to–Digital Operation
If CCI is 24 times the frequency of MSI, short cycle ana-
log–to–digital operation is selected. This allows a 13–bit A/D
conversion only. In this mode, the D/A is not operational and
any data applied to the RDD input is ignored.
Short Cycle Digital–to–Analog Operation
Short cycle digital–to–analog operation is selected by
using a CCI clock frequency that is eight times the MSI sam-
ple rate. During short cycle D/A operation, A/D operation is
disabled and digital data read from TDD is not valid.
CLOCKING RECOMMENDATIONS
For optimum differential nonlinearity performance, all data
transitions on TDD and RDD should be limited to the first four
CCI cycles following the rising edge of MSI. This may be
achieved by setting MSI = TDE = RCE having a duration of
16 data clock cycles, and TDC = RDC ≥ 4 x CCI clock
MOTOROLA
frequency. Figure 6 shows a circuit that generates this clock-
ing configuration; see Application Circuits section.
SIGNAL TO DISTORTION RATIO
Figures 4 and 5 show graphs of typical signal to distortion
ratios versus signal level for the MC145402. The presented
data is referenced to a 1020 Hz input sinusoidal frequency
with signal levels referenced to 600 Ω and transmission level
point adjusted (e.g., 0 dBm0 at 600 Ω with a TLP of 6.30 dB
is 4.53 V peak–to–peak). For comparison, ideal signal to
noise ratios for 9–, 10–, 11–, 12–, and 13–bit A/D and D/A
converters are also shown. The equation used for an ideal
RMS to RMS signal to distortion ratio is:
S/D = N x 6 dB + 1.76 dB
where N is the number of bits of resolution, 6 dB per bit, and
1.76 = 20log (√3/√2).
(√3/√2) is approximately the RMS to RMS ratio of a sine
wave to white noise.
The signal to noise plus distortion ratio is measured
through a brickwall low–pass filter set to the Nyquist frequen-
cy of the A/D and D/A sample rate. For an 8 kHz sample rate,
the low–pass filter is set to block all signals above 4 kHz.
APPLICATION CIRCUITS
Figure 6 shows a typical circuit for generating the clock
frequencies for the MC145402. This circuit uses an
MC74HC4040 and a 2.048 MHz crystal to generate the
256 kHz frequency for internal sequencing, 1.024 MHz for
the date clocks, and an 8 kHz sample frequency. A
4.096 MHz crystal could be used for a sample rate of 16 kHz.
Figure NO TAG shows the MC145402 interfaced to the
DSP56000 digital signal processor. The DSP56000 can in-
ternally generate the clocks for the MC145402 using the SSI
serial interface. SCK provides the sequencing and data
clocks (non–gated continuous dock) and SC2 (setup as the
Frame Sync Out, FSL = 0) provides the sample rate and data
enables for the MC145402. The divide–by–four circuit to
generate the CCI clock is recommended for optimum
MC145402 performance, and allows the DSP56000 to clock
data in and out of the MC145402 quickly, leaving time avail-
able for processing by the DSP before another sample is
available. SC0 and SC1 could be used to gate the enables to
select up to four devices on the SSI bus.
TELEPHONE SYSTEM TRANSMISSION LEVEL POINT
FOR A LINEAR A/D OR D/A CONVERTER
REFERENCED TO MU–LAW COMPANDING
Mu–Law companding, as specified by AT&T and CCITT,
requires 8159 quantization levels to implement both A/D and
D/A conversion schemes. This is to be mirrored about signal
ground for the negative part of the wave form.
To implement a 13–bit (± 12–bit) linear converter scheme
requires 8192 quantization levels mirrored about signal
ground. To specify this converter such that it can be used to
interface with, or as an alternative to, telephony based Mu–
Law applications, the following is an explanation of the gain
translation.
A 13–bit linear converter scheme has 8192 quantization
levels. The goal is to be able to convert between these two
encoding schemes with minimal distortion. This dictates set-
ting the LSBs to the same level. For this to be achieved re-
quires the reference voltage of the linear converter to be
MC145402
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