ERRATA 데이터 시트보기 (PDF) - STMicroelectronics
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ERRATA Datasheet PDF : 4 Pages
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ST10F280-AB
2.4 - ST_XTIMER.01 - XADCINJ Signal Output Too Short for ADC Channel Injection
The duration of the XADCINJ output lasts two cycles (50ns at 40MHz) but to ensure that a signal
transition is properly recognized, an external capture input signal should be held for at least 8 CPU clock
cycles before it changes its level so the duration of the XADCINJ signal is too short.
Figure 1 : XADCINJ Timing
XCLK
XADCINJ
4 TCL = 50ns
Workaround:
The falling edge of the XADCINJ signal must be delayed up to 8 CPU clock cycles.
Figure 2 : External Connection for ADC Channel Injection
CAPCOM2 UNIT
Clock
P7.7/CC31
Input
Latch
Output trigger for ADC
channel injection
XTIMER
XADCINJ
R
C Typical value:
R = 10KΩ C = 47pF at 40MHz
History of Fixed Functional Problems of the ST10F280
Name
Short Description
Fixed in Step
ST_XADCMUX.01 Erroneous Conversion Result in Overload Condition
AB
Summary of Remaining Functional Problems Known on the ST10F280-AB
Name
Short Description
PWRDN.1
MAC.9
MAC.10
ST_XTIMER.01
Execution of PWRDN Instruction
CoCMP Instruction Inverted Operands
E Flag Evaluation for CoSHR and CoASHR Instructions when Saturation Mode is Enabled
XADCINJ Signal Output Too Short for ADC Channel Injection
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