LRS1331 데이터 시트보기 (PDF) - Sharp Electronics
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LRS1331 Datasheet PDF : 26 Pages
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LRS1331
Stacked Chip (16M Flash & 4M SRAM)
Table 2. Truth Table1
FLASH
Read
Output Disable
Write
Standby
Reset
Standby
Reset
SRAM
Standby
Standby
F-CE
L
L
F-RP
H
H
F-OE
L
H
F-WE
H
H
S-CE1 S-CE2
See Note 4
S-OE
X
X
S-WE
X
X
S-LB S-UB
See Note 4
DQ0 - DQ8 -
DQ7 DQ15
DOUT
HIGH-Z
Standby L
H
H
L
X
X
Read
H
H
X
X
L
H
L
H
DIN
See Note 7
Output
H
H
X
X
L
H
H
H
X
X
HIGH-Z
Disable H
H
X
X
L
H
X
X
H
H
HIGH-Z
Write
H
H
X
X
L
H
L
L
Read
X
L
X
X
L
H
L
H
See Note 7
Output
X
L
X
X
L
H
H
H
X
X
HIGH-Z
Disable X
L
X
X
L
H
X
X
H
H
HIGH-Z
Write
X
L
X
X
L
H
L
L
See Note 7
Standby H
H
X
X
X
X
HIGH-Z
See Note 4
See Note 4
Standby X
L
X
X
X
X
HIGH-Z
NOTES
2, 3
3
2, 3, 5, 6
3
3
NOTES:
1. L = VIL, H = VIH, X = H or L. Refer to DC Characteristics.
2. Refer to the ‘Flash Memory Command Definition’ section for valid
address input and DIN during a write operation.
3. F-WP set to VIL or VIH.
4. SRAM standby data. See Table 2a.
5. Command writes involving block erase or word write are reliably
executed when VCCWH (2.7 V to 3.6 V) and F-VCC = 2.7 V to
3.6 V. Block erase or word write with F-VCCW < VCCWH (MIN.)
produce spurious results and should not be attempted.
6. Never hold F-OE LOW and F-WE LOW at the same timing.
7. S-LB, S-UB Control Mode. See Table 2b.
MODE
Standby
(SRAM)
S-CE1
H
X
X
Table 2a.
PINS
S-CE2
S-LB
X
X
L
X
X
H
S-UB
X
X
H
MODE
(SRAM)
Read/Write
S-LB
L
L
H
Table 2b.
S-UB
L
H
L
PINS
DQ0 - DQ7
DOUT/DIN
DOUT/DIN
HIGH-Z
DQ8 - DQ15
DOUT/DIN
HIGH-Z
DOUT/DIN
4
Data Sheet
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