XWM8722EDS 데이터 시트보기 (PDF) - Wolfson Microelectronics plc

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XWM8722EDS

Stereo DAC with Integrated Tone Generator and Line/Variable Level Outputs

Wolfson Microelectronics plc 

WM8722

SYSTEM CLOCK

Advanced Information

TONE GENERATOR DAC

The tone generator comprises a digital frequency synthesiser, which is used to create a clock at 128x

the required tone frequency, and a 128 step per cycle, sine weighted DAC, which converts the clock

into one of three tone types. An analogue programmable gain stage follows the DAC, allowing gain

adjustment of the tone amplitude. Noise shaping techniques are used to create minimal spurious

components in the frequency synthesiser.

The WM8722 can generate three different tone types. The default setting is a sinusoidal tone.

Square waves are generated by setting the SQR bit. Alternatively, a two-tone output that generates

one cycle at the chosen frequency, followed by two cycles at twice that frequency can be selected by

setting the F2F bit. This facility may be used in sine or square wave modes.

The frequency of the resulting tone is controllable with 1Hz resolution, over a range of 1Hz to

32.767kHz, based on a TCLK frequency of 27MHz. Alternative tone clock frequencies may be used if

required. For example the DAC SCLK frequency may be used, but in these cases the frequency

range and resolution will change by the ratio of the clock used, to the nominal 27MHz clock specified.

The duration of the selected tone is programmed via the serial interface. Once both the frequency

and the duration have been set to non-zero values, the tone generation commences. Once the tone

generator has started running, the next tone frequency and duration may be programmed ready to

start as soon as the current tone finishes. Under this condition the tones are phase continuous, and a

BUSY flag is set on the BUSY pin, which now becomes a CMOS output, overdriving any pull-up or

down resistor placed on the pin to select the interface format at power-up. After a tone frequency of

duration has been written, it may be over written with a new value if desired.

At the conclusion of a tone burst, the circuit ensures that at the end of the duration time of the last

tone, the tone continues to the next zero crossing point to ensure DC offsets are not created. A

control bit (TFIN) is provided which allows selection of the method of completion of the burst: If set to

1, the burst completes at the next zero crossing. If left at 0, the burst completes a whole number of

sinusoids, avoiding potential problems with DC levels changing across AC coupling capacitors.

Whilst tones are being generated, writing either new frequency or new duration, will cause the

subsequent burst to be generated phase continuously with the current burst. If a duration value of 0

is written during a burst, the current burst will stop immediately (at the next zero cross or full cycle

complete point as selected by TFIN).

If the current burst completes, and no new duration of frequency have been set, the tones stop and

the duration value is reset to zero. The frequency setting is maintained in volatile memory. If a new

duration is programmed, then the tone generator will re-start with the previously programmed

frequency. If a new frequency is desired, the frequency is simply programmed before the duration,

the tone commencing when the duration is written.

The system clock for the WM8722 must be either 256fs or 384fs where fs is the audio sampling

frequency (LRCIN), typically 32kHz, 44.1kHz, 48kHz or 96kHz. The system clock is used to operate

the digital filters and the noise shaping circuits.

WM8722 has system clock detection circuitry that automatically determines the relationship between

the system clock frequency and the sampling rate (to within 8 system clocks). If greater than 8 clocks

error, then the interface shuts down the DAC and mutes the output. The system clock should be

synchronised with LRCIN, but WM8722 is tolerant of phase differences or jitter on this clock. Severe

distortion in the phase difference between LRCIN and the system clock (for example caused by too

many or too few system clocks received per LRCIN period) will be detected, and cause the device to

automatically re-synchronise. If the externally applied LRCIN slips in phase by more than half the

internal LRCIN period, which is derived from the master clock, then the interface resynchronises.

During re-synchronisation, the WM8722 will either repeat the previous sample or drop the next

sample depending on the nature of the phase slip. This will ensure there is no discernible click at the

analogue outputs during re-synchronisation.

WOLFSON MICROELECTRONICS LTD

AI Rev 1.5 May 2000

10

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