EL1881C 데이터 시트보기 (PDF) - Elantec -> Intersil

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EL1881C

Sync separator, low power

Elantec -> Intersil 

EL1881C

Sync Separator, Low Power

Applications Information

Video In

A simplified block diagram is shown following page.

An AC coupled video signal is input to Video In pin 2

via C1, nominally 0.1µF. Clamp charge current will pre-

vent the signal on pin 2 from going any more negative

than Sync Tip Ref, about 1.5V. This charge current is

nominally about 1mA. A clamp discharge current of

about 10µA is always attempting to discharge C1 to

Sync Tip Ref, thus charge is lost between sync pulses

that must be replaced during sync pulses. The droop

voltage that will occur can be calculated from IT = CV,

where V is the droop voltage, I is the discharge current,

T is the time between sync pulses (sync period - sync tip

width), and C is C1.

An NTSC video signal has a horizontal frequency of

15.73kHz, and a sync tip width of 4.7µs. This gives a

period of 63.6µs and a time T = 58.9µs. The droop volt-

age will then be V = 5.9mV. This is less than 2% of a

nominal sync tip amplitude of 286mV. The charge rep-

resented by this droop is replaced in a time given by T =

CV/I, where I = clamp charge current = 1mA. Here T =

590ns, about 12% of the sync pulse width of 4.7µs. It is

important to choose C1 large enough so that the droop

voltage does not approach the switching threshold of the

internal comparator.

Fixed Gain Buffer

The clamped video signal then passes to the fixed gain

buffer which places the sync slice level at the equivalent

level of 70mV above sync tip. The output of this buffer

is presented to the comparator, along with the slice refer-

ence. The comparator output is level shifted and

buffered to TTL levels, and sent out as Composite Sync

to pin 1.

Burst

A low-going Burst pulse follows each rising edge of

sync, and lasts approximately 3.5µs for an RSET of

681kΩ.

Vertical Sync

A low-going Vertical Sync pulse is output during the

start of the vertical cycle of the incoming video signal.

The vertical cycle starts with a pre-equalizing phase of

pulses with a duty cycle of about 93%, followed by a

vertical serration phase that has a duty cycle of about

15%. Vertical Sync is clocked out of the EL1881C on

the first rising edge during the vertical serration phase.

In the absence of vertical serration pulses, a vertical sync

pulse will be forced out after the vertical sync default

delay time, approximately 60µS after the last falling

edge of the vertical equalizing phase for RSET = 681kΩ.

Odd/Even

Because a typical television picture is composed of two

interlaced fields, there is an odd field that includes all

the odd lines, and an even field that consists of the even

lines. This odd/even field information is decoded by the

EL1881C during the end of picture information and the

beginning of vertical information. The odd/even circuit

includes a T-flip-flop that is reset during full horizontal

lines, but not during half lines or vertical equalization

pulses. The T-flip-flop is clocked during each falling

edge of these half hperiod pulses. Even fields will toggle

until a low state is clocked to the odd/even pin 7 at the

beginning of vertical sync, and odd fields will cause a

high state to be clocked to the odd/even pin at the start of

the next vertical sync pulse. Odd/even can be ignored if

using non-interlaced video, as there is no change in tim-

ing from one field to the next.

RSET

An external RSET resistor, connected from RSET pin 6 to

ground, produces a reference current that is used inter-

nally as the timing reference for vertical sync width,

vertical sync default delay, burst gate delay and burst

width. Decreasing the value of RSET increases the refer-

ence current, which in turn decreases reference times

and pulse widths. A higher frequency video input neces-

sitates a lower RSET value.

Chroma Filter

A chroma filter is suggested to increase the S/N ratio of

the incoming video signal. Use of the optional chroma

filter is shown in Figure 5. It can be implemented very

simply and inexpensively with a series resistor of 620Ω

and a parallel capacitor of 500pF, which gives a single

10

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