SK100EL15WD 데이터 시트보기 (PDF) - Semtech Corporation
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SK100EL15WD Datasheet PDF : 4 Pages
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HIGH-PERFORMANCE PRODUCTS
Description
Features
SK10/100EL15W
1:4 Clock
Distribution
The SK10/100EL15W is a low skew 1:4 clock distribution •
chips designed explicitly for low skew clock distribution
applications. This device is fully compatible with
MC10EL15 & MC100EL15. The device can be driven by •
either a differential or single-ended ECL or, if positive power •
supplies are used, PECL input signal. If a single-ended •
input is to be used, the VBB output should be connected •
to the CLK* input and bypassed to VCC via a 0.01 µF •
capacitor. The EL15W provides a VBB output for either •
single-ended use or as a DC bias for AC coupling to the
device. The VBB pin should be used only as a bias for •
EL15W as its current sink/source capability is limited. •
Whenever used, the VBB pin should be bypassed to VCC
via a 0.01 µF capacitor.
Extended Supply Voltage Range: (VEE = –5.5V to
–3.0V, VCC = 0V) or (VCC = + 3.0V to +5.5V,
VEE=0V)
50 ps Output-to-Output Skew
Synchronous Enable/Disable
Multiplexed Clock Input
Internal 75KW Input Pull-Down Resistors
Fully Compatible with MC10/100EL15
Specified Over Industrial Temperature Range:
–40oC to +85oC
ESD Protection of >4000V
Available in 16 Lead SOIC Package
The EL15W features a multiplexed clock input to allow for
the distribution of a lower speed scan or test clock along
with the high speed system clock. When LOW (or left
open and pulled LOW by the input pull-down resistor) the
SEL pin will select the differential clock input.
The common enable (EN*) is synchronous so that the
outputs will only be enabled/disabled when they are already
in the LOW state. This avoids any chance of generating a
runt clock pulse when the device is enabled/disabled as
can happen with an asynchronous control. The internal
flip-flop is clocked on the falling edge of the input clock,
therefore, all associated specification limits are referenced
to the negative edge of the clock input.
PIN Description
Pin Name
CLK
SCLK
EN*
SEL
VBB
Function
Differential Clock Inputs
Synchronous Clock Input
Synchronous Enable
Clock Select Input
Reference Output Voltage
Functional Block Diagram
Q0–Q3, Q0*-Q3* Differential Clock Outputs
Q0 1
Q0* 2
Q1 3
Q1* 4
Q2 5
Q2* 6
Q3 7
Q3* 8
QD
16 VCC
15 EN*
14 SCLK
1
13 CLK
0
12 CLK*
11 VBB
10 SEL
9 VEE
Revision 1/August 23, 2001
CLK
SCLK
SEL
EN*
Q
L
X
L
L
L
H
X
L
L
H
X
L
H
L
L
X
H
H
L
H
X
X
X
H
L*
*On next negative transition of CLK or SCLK.
Truth Table
1
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