DS2175 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2175

T1/CEPT Elastic Store

Dallas Semiconductor -> Maxim Integrated 

DS2175

DS2175

T1/CEPT Elastic Store

FEATURES

• Rate buffer for T1 and CEPT transmission systems

• Synchronizes loop–timed and system timed data

streams on frame boundaries

• Ideal for T1 (1.544 MHz) to CEPT (2.048 MHz), CEPT

to T1 interfaces

• Supports parallel and serial backplanes

• Buffer depth is 2 frames

• Comprehensive on–chip “slip” control logic

– Slips occur only on frame boundaries

– Outputs report slip occurrences and direction

– Align feature allows buffer to be recentered at

any time

– Buffer depth easily monitored

• Compatible with DS2180A T1 and DS2181A CEPT

Transceivers

• Industrial temperature range of –40°C to +85°C avail-

able, designated DS2175N

PIN ASSIGNMENT

RCLKSEL 1

RCLK 2

RSER 3

RMSYNC 4

FSD 5

SLIP 6

ALN 7

VSS 8

16 VDD

15 SYSCLK

14 SSER

13 SMSYNC

12 SFSYNC

11 SCHCLK

10 S/P

9 SCLKSEL

16–PIN DIP (300 MIL)

16–PIN SOIC (300 MIL)

DESCRIPTION

The DS2175 is a low–power CMOS elastic–store

memory optimized for use in primary rate telecommu-

nications transmission equipment. The device serves

as a synchronizing element between async data

streams and is compatible with North American

(T1–1.544 MHz) and European (CEPT–2.048 MHz)

rate networks. The chip has several flexible operating

modes which eliminate support logic and hardware cur-

rently required to interconnect parallel or serial TDM

backplanes. Application areas include digital trunks,

drop and insert equipment, digital cross–connects

(DACS), private network equipment and PABX–to–

computer interfaces such as DMI and CPI.

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