DS2175 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2175

T1/CEPT Elastic Store

Dallas Semiconductor -> Maxim Integrated 

RECEIVE SIDE TIMING (RCLK = 1.544 MHz) Figure 2

RCLK

RMSYNC

RSER

LSB MSB

CHANNEL 24

LSB F MSB

DS2175

LSB

CHANNEL 1

RECEIVE SIDE TIMING (RCLK = 2.048 MHz) Figure 3

RCLK

RMSYNC

RSER1

LSB MSB

LSB MSB

LSB

CHANNEL 32

CHANNEL 1

NOTES:

1. All channel data is passed through the elastic store in 2.048 MHz system side applications (SCLKSEL = 1);

2. Data in channels >24 is ignored in 1.544 MHz system side applications (SCLKSEL = 0).

SYSTEM MULTIFRAME BOUNDARY TIMING (SYSCLK = 1.544 MHz) Figure 4

SYSCLK

SFSYNC

SMSYNC

SCHCLK

SSER1

LSB MSB

LSB F MSB

LSB

(S/P=1)

CHANNEL 24

CHANNEL 1

SSER1

(S/P=0)

LSB F MSB

LSB MSB

LSB

CHANNEL 1

CHANNEL 2

022798 5/12

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