DS2175 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2175

T1/CEPT Elastic Store

Dallas Semiconductor -> Maxim Integrated 

DS2175

NOTES:

1. In 1.544 MHz receive side applications (RCLKSEL=0), the F–bit position contains F–bit data extracted from the

data stream at RSER. The F–bit position is forced to “1” in 2.048 MHz receive side applications (RCLKSEL=1).

2. In 2.048 MHz receive side applications (RCLKSEL=1), the E–bit position is forced to “1” and data in channels

>24 is ignored.

SYSTEM MULTIFRAME BOUNDARY TIMING (SYSCLK = 2.048 MHz) Figure 5

SYSCLK

SFSYNC

SMSYNC

SCHCLK

SSER1

(S/P=1)

LSB MSB

LSB MSB

LSB

CHANNEL 32

CHANNEL 1

SSER1

(S/P=0)

LSB MSB

LSB MSB

LSB

CHANNEL 1

CHANNEL 2

NOTES:

1. In 2.048 MHz receive side applications (RCLKSEL=1), all channel data is passed through the elastic store.

2. In 1.544 MHz receive side applications (RCLKSEL=0), all channel data is passed through the elastic store, except

the F–bit position which is ignored. Data in channels >24 on the system side is forced to all ones.

022798 6/12

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