SAA7780 데이터 시트보기 (PDF) - Philips Electronics
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SAA7780 Datasheet PDF : 70 Pages
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Philips Semiconductors
ThunderBird Q3D PCI Audio
Accelerator
Product Specification
SAA7780
C/BE#[3:0]
DEVSEL#
FRAME#
IRDY#
STOP#
50,65,76,88 IO-T
PCI Bus Command and Byte Enables
C/BE#[3:0] defines the bus command during the first clock of a PCI
transaction, and the byte enables during subsequent clocks.
C/BE#[3:0] are outputs when the SAA7780 is a PCI bus master and
inputs when it is a PCI bus slave.
70
IO-STS PCI Bus Device Select
When the SAA7780 is a PCI bus master the SAA7780 uses
DEVSEL# to determine whether a master abort should occur if
DEVSEL# is not sampled active by clock 5 of the transaction, or to
determine whether a cycle is to be aborted or retried when a target-
initiated termination occurs.
When the SAA7780 is a PCI bus slave, DEVSEL# is an output
which the SAA7780 drives LOW during the second PCLK after
FRAME# assertion to the end of a transaction if the SAA7780 is
selected.
66
IO-STS PCI Bus Cycle Frame
When the SAA7780 is a PCI master, FRAME# is an output which
indicates the beginning of a SAA7780-initiated bus transaction.
While FRAME# is asserted data transfers continue. When FRAME#
is deasserted the transaction is in the final data phase.
When the SAA7780 is a PCI slave, FRAME# is an input that initiates
an I/O, memory or configuration register access if the SAA7780 is
selected for the transaction. The SAA7780 latches the C/BE#[3:0]
and AD[31:0] signals on the PCLK edge on which it first samples
FRAME# active.
67
IO-STS PCI Bus Initiator Ready
When the SAA7780 is a PCI master, IRDY# is an output which
indicates the SAA7780’s ability to complete the data phase of the
current transaction. It is always asserted from the PCLK cycle after
FRAME# is asserted to the last clock of the transaction.
When the SAA7780 is a PCI slave, IRDY# is an input which causes
the SAA7780 to hold-off completion of a read or write cycle until
sampled active.
71
IO-STS PCI Bus Stop (Target Initiated Termination)
When the SAA7780 is a PCI master, STOP# is an input which
causes the SAA7780 to complete, abort or retry the transfer,
depending on the state of TRDY# and DEVSEL#.
When the SAA7780 is a PCI slave, it drives STOP# as active (LOW)
to terminate or retry a transaction.
1999 Sep 30
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