WM2148 데이터 시트보기 (PDF) - Wolfson Microelectronics plc
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WM2148 Datasheet PDF : 14 Pages
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Production Data
WM2148
ADDRESS
A1
0
0
1
0
2
1
3
1
Table 2 WM2148 Internal Registers
A0
REGISTER
0
ADC Conversion Result
1
PGA gain
0
DC Offset
1
Control
The ADC data register contains the result of the last analogue to digital conversion. It can also be
used to reset the device to its default state by writing a ‘1’ to the LSB (D0). This will set all the bits in
the gain, offset and control registers to ‘0’. All other bits should always be set to zero when writing to
the ADC data register.
The PGA gain is controlled using the last three bits of Address 1. The eight possible binary values of
000 to 111 (decimal 7) correspond to a gain of 0 to 7dB, respectively.
The lower byte of Address 2 holds the offset value (in LSBs). This value is added to the ADC data if
the DCO bit in the Control register is set. The offset is in Two’s complement format, providing a
range of -128 to +127 LSB.
REG. / BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ADC Data MSB …
…
…
…
…
…
…
…
…
…
…
… LSB/
SR
PGA Gain
X
X
X
X
X
X
X
X
X
X
X
G2 G1 G0
DC Offset
X
X
X
X
X
X MSB …
…
…
…
…
… LSB
Control
PWD REF FOR TM2 TM1 TM0 DCO X
X
X
X
X
X
X
Table 3 WM2148 Register Map
The Control register (address 3) has four bits to program the device’s operation and three test mode
bits. Setting the Power Down bit (PWD) takes the device into Power Down mode. DCO enables the
addition of the offset value held at Address 2 to the ADC output data. REF selects between internal
and external reference voltages, and FOR between unsigned binary and Two’s complement output
format.
BIT
DESCRIPTION
PWD
Power Down
REF
Reference Select
FOR
Output Format
DCO
DC Offset
SR
Software Reset
X
Reserved
Table 4 Control Bits and Software Reset
0
1
Normal Operation
Power Down
Internal Reference
External Reference
Unsigned Binary
Two’s Complement
Enable
Disable
Normal Operation
Reset
Always set to 0 when writing to any register.
The ADC core can be tested by selecting one of six different test modes, which apply various
voltages to the analogue inputs. This may be useful for calibration purposes. The test modes are
controlled by the three test mode bits in the control register, TM0 to TM2 (see Table 5 below).
TM2
TM1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Table 5 Test Modes
TM0
0
1
0
1
0
1
0
1
FUNCTION
Normal Operation
Both inputs = REF-
IN+ at Vref/2, IN- at REF-
IN+ at REF+, IN- at REF-
Normal Operation
Both inputs = REF+
IN+ at REF-, IN- at Vref/2
IN+ at REF-, IN- at REF+
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 February 2001
9
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