MXL1016 데이터 시트보기 (PDF) - Maxim Integrated
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MXL1016 Datasheet PDF : 4 Pages
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Ultra-Fast Precision TTL Comparators
ELECTRICAL CHARACTERISTICS – MXL1116
(V+ = 5V, V– = –5V, VOUT (Q) = 1.4V, VLE = 0V, TA = TMIN to TMAX, unless otherwise noted. Specifications for VOS, IB, CMRR and AV
are valid for single-supply operation, V+ = 5V, V– = 0V.)
PARAMETER
Input Offset Voltage
(Note 1)
Input Offset-Voltage Drift
Input Offset Current
(Note 1)
Input Bias Current, Sourcing
(Note 2)
SYMBOL
VOS
RS ≤ 100Ω
∆VOS/∆T
IOS
IB
CONDITIONS
TA = +25°C
Input Voltage Range
Common-Mode Rejection Ratio
Power-Supply Rejection Ratio
Small-Signal Voltage Gain
Output High Voltage
Output Low Voltage
Positive Supply Current
Negative Supply Current
Latch Pin High Input Voltage
Latch Pin Low Input Voltage
Latch Input Current
Propagation Delay
(Note 3)
VCM
CMRR
PSRR
AV
VOH
VOL
I+
I–
VIH
VIL
IIL
tPD
Single 5V supply
–5V ≤ VCM ≤ 2.5V
0V ≤ VCM ≤ 2.5V, VS = +5V, 0V
Positive Supply: 4.6V ≤ V+ ≤ 5.4V
Negative Supply: –7V ≤ V– ≤ –2V
1V ≤ VOUT ≤ 2V, TA = +25°C
ISOURCE = 1mA
ISOURCE = 10mA
ISINK = 4mA
ISINK = 10mA, TA = +25°C
VLE = 0V
∆VIN = 100mV,
OD = 5mV
∆VIN = 100mV,
OD = 20mV
TA = +25°C
TA = +25°C
Differential Propagation Delay
(Note 3)
Latch Setup Time (Note 4)
Latch Hold Time (Note 4)
∆tPD
tSU
tH
∆VIN = 100mV, OD = 5mV, TA = +25°C
MIN TYP MAX UNITS
1.0
±3
mV
3.5
5
µV/°C
0.5
2
µA
V–
0
75
65
60
80
1400
2.7
2.4
2.0
10
20
µA
(V+ – 2.5)
V
2.5
90
dB
90
75
dB
100
3000
V/V
3.4
V
3.0
0.3
0.5
V
0.4
27
38
mA
5
7
mA
V
0.8
V
–20 –500 µA
12
16
18
ns
10
14
16
3
ns
2
ns
2
ns
Note 1: Input offset voltage is defined as the average of the two input offset voltages, measured by forcing first one output, then the
other to 1.4V. Input offset current is defined in the same way.
Note 2: Input bias current (IB) is defined as the average of the two input currents.
Note 3: tPD and ∆tPD cannot be measured in automatic handling equipment with low values of overdrive. Correlation tests have
shown that tPD and ∆tPD limits shown can be guaranteed by design, if additional DC tests are performed to guarantee that
all internal bias conditions are correct. For low overdrive conditions, VOS is added to overdrive.
Note 4: Input latch setup time, tSU, is the interval in which the input signal must be stable prior to asserting the latch signal. The hold
time, tH, is the interval after the latch is asserted in which the input signal must be stable.
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