FX613 데이터 시트보기 (PDF) - CML Microsystems Plc
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FX613 Datasheet PDF : 8 Pages
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Application Information ......
Decoder Timing
CHIP SELECT
tCSE
tCYC
tCSH
SERIAL CLOCK
tDE
tPWL
tPWH
tCDS
tDH
DATA OUT
TRI-STATE
BIT 5
BIT 4
tHIZ
BIT 0
tIR
IRQ
Fig.4 Data-Read Timing
Decoder Timing Characteristics
With reference to Figure 4, Data-Read Timing.
Characteristics
t
Serial Clock “High” Pulse Width
PWH
tPWL
Serial Clock “Low” Pulse Width
tCYC
Serial Clock-Cycle Time
tCSE
Chip Select Low to Clock “High” Edge
tCSH
Last Clock “High” Edge to CS “High”
tDH
Data Out Hold Time
tCDS
Clock Edge to Data Out Set Time
t
Interrupt (IRQ) Reset Time
IR
tDE
Chip Select “Low” to Data Enable
tHIZ
Chip Select “High” to Output Tri-State
Min.
250
250
600
450
600
0
-
-
-
-
Typ.
-
-
-
-
-
-
-
-
-
-
Max.
-
-
-
-
-
-
200
200
200
1000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1 Data is output bit 5 first. Bit 5 can be clocked into the µProcessor by the first Serial Clock rising edge.
If 8 Serial Clock pulses are employed the last 2 data-bits will be “0” and should be ignored by the
software.
2 Chip Select should be used to react to Interrupts and then returned to a logic “1”.
If Chip Select stays low there will be no further Interrupts and no Data Output update.
6
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