N80930AD4 데이터 시트보기 (PDF) - Intel

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N80930AD4

UNIVERSAL SERIAL BUS MICROCONTROLLER

Intel 

8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER

3.0 SIGNALS

Table 5. Signal Descriptions

Signal

Name

Type

Description

Alternate Function

A17

O 18th Address Bit (A17). Output to memory as 18th exter- P1.7/CEX4/WCLK

nal address bit (A17) in extended bus applications, depend-

ing on the values of bits RD0 and RD1 in configuration byte

UCONFIG0. See also RD#, PSEN#.

A16

A15:8†

AD7:0†

O Address Line 16. See RD#.

RD#

O Address Lines. Upper address lines for the external bus. P2.7:0

I/O Address/Data Lines. Multiplexed lower address lines and P0.7:0

data lines for external memory.

ALE

O Address Latch Enable (ALE). ALE signals the start of an PROG#

external bus cycle and indicates that valid address informa-

tion is available on lines A15:8 and AD7:0. An external latch

can use ALE to demultiplex the address from the

address/data bus.

AVCC

PWR Analog VCC. A separate VCC input for the phase-locked loop

circuitry.

CEX2:0

CEX3

CEX4

I/O Programmable Counter Array (PCA) Input/Output Pins. P1.5:3

These are input signals for the PCA capture mode and out- P1.6/WAIT#

put signals for the PCA compare mode and PCA PWM

P1.7/A17/WCLK

mode.

DM0

I/O Data Minus. USB minus data line interface.

—

DP0

I/O Data Plus. USB plus data line interface.

—

EA#

I External Access. Directs program memory accesses to

on-chip or off-chip code memory. For EA# strapped to

ground, all program memory accesses are off-chip. For EA#

strapped to VCC, program accesses on-chip ROM if the

address is within the range of the on-chip ROM; otherwise,

the access is off-chip. The value of EA# is latched at reset.

For devices without on-chip ROM, EA# must be strapped to

ground.

ECAP

ECI

I External Capacitor. Must be connected to a 1 µF capacitor

(or larger) to ensure proper operation of the differential line

driver. The other lead of the capacitor must be connected to

VSS.

I PCA External Clock Input. External clock input to the 16- P1.2

bit PCA timer.

INT1:0#

I External Interrupts 0 and 1. These inputs set bits IE1:0 in P3.3:2

the TCON register. If bits IT1:0 in the TCON register are

set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If

bits INT1:0 are clear, bits IE1:0 are set by a low level on

INT1:0#.

P0.7:0

I/O Port 0. This is an 8-bit, open-drain, bidirectional I/O port. AD7:0

† The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration. If the

chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 car-

ries the upper address bits (A15:8) and the data (D7:0).

ADVANCE INFORMATION

7

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