AD650KP 데이터 시트보기 (PDF) - Analog Devices
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AD650KP Datasheet PDF : 12 Pages
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AD650
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
Storage Temperature Ceramic . . . . . . . . . . . . –55°C to +165°C
Storage Temperature Plastic . . . . . . . . . . . . . –25°C to +125°C
Differential Input Voltage (Pins 2 and 3) . . . . . . . . . . . . ± 10 V
Maximum Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS
Open Collector Output Voltage Above Digital GND . . . . . 36 V
Open Collector Output Current . . . . . . . . . . . . . . . . . . 50 mA
Amplifier Short Circuit to Ground . . . . . . . . . . . . . . . Indefinite
Comparator Input Voltage (Pin 9) . . . . . . . . . . . . . . . . . . . ± VS
ORDERING GUIDE
Model1
Gain
Tempco
ppm/ ؇C
100 kHz
1 MHz
Linearity
Specified
Temperature
Range ؇C
Package
AD650JN 150 typ
AD650KN 150 typ
AD650JP 150 typ
AD650KP 150 typ
AD650AD 150 max
AD650BD 150 max
AD650SD 150 max
0.1% typ 0 to +70
0.1% max 0 to +70
0.1% typ 0 to +70
0.1% max 0 to +70
0.1% typ –25 to +85
0.1% max –25 to +85
0.1% max –55 to +125
Plastic DIP
Plastic DIP
PLCC
PLCC
Ceramic
Ceramic
Ceramic
NOTE
1For details on grade and package offerings screened in accordance with
MIL-STD-883B, refer to the Analog Devices Military Products Databook or
current AD650/883B data sheet.
CIRCUIT OPERATION
UNIPOLAR CONFIGURATION
The AD650 is a charge balance voltage-to-frequency converter.
In the connection diagram shown in Figure 1, or the block dia-
gram of Figure 2a, the input signal is converted into an equiva-
lent current by the input resistance RIN. This current is exactly
balanced by an internal feedback current delivered in short,
timed bursts from the switched 1 mA internal current source.
These bursts of current may be thought of as precisely defined
packets of charge. The required number of charge packets, each
producing one pulse of the output transistor, depends upon the
amplitude of the input signal. Since the number of charge pack-
ets delivered per unit time is dependent on the input signal am-
plitude, a linear voltage-to-frequency transformation will be
accomplished. The frequency output is furnished via an open
collector transistor.
A more rigorous analysis demonstrates how the charge balance
voltage-to-frequency conversion takes place.
A block diagram of the device arranged as a V-to-F converter is
shown in Figure 2a. The unit is comprised of an input integra-
tor, a current source and steering switch, a comparator and a
one-shot. When the output of the one-shot is low, the current
steering switch S1 diverts all the current to the output of the op
amp; this is called the Integration Period. When the one-shot
has been triggered and its output is high, the switch S1 diverts
all the current to the summing junction of the op amp; this is
called the Reset Period. The two different states are shown in
Figure 2 along with the various branch currents. It should be
noted that the output current from the op amp is the same for
either state, thus minimizing transients.
PIN CONFIGURATION
PIN “D”
NO. CERAMIC DIP
PACKAGE
“N”
PLASTIC DIP
“P”
PLCC
1
VOUT
2 +IN
3 –IN
VOUT
+IN
–IN
NC
VOUT
+IN
4 BIPOLAR OFFSET BIPOLAR OFFSET –IN
CURRENT
CURRENT
5 –VS
6 ONE SHOT
–VS
ONE SHOT
NC
BIPOLAR OFFSET
CAPACITOR
CAPACITOR
CURRENT
7 NC
NC
NC
8
FOUTPUT
9 COMPARATOR
FOUTPUT
COMPARATOR
–VS
ONE SHOT
INPUT
INPUT
CAPACITOR
10 DIGITAL GND
DIGITAL GND
NC
11 ANALOG GND
ANALOG GND
NC
12 +VS
13 OFFSET NULL
+VS
OFFSET NULL
FOUTPUT
COMPARATOR
INPUT
14 OFFSET NULL
OFFSET NULL
DIGITAL GND
15
NC
16
ANALOG GND
17
NC
18
+VS
19
OFFSET NULL
20
OFFSET NULL
Figure 1. Connection Diagram for V/F Conversion,
Positive Input Voltage
Figure 2a. Block Diagram
REV. A
–3–
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