HT82K28A 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT82K28A

Win98 Keyboard Encoder

Holtek Semiconductor 

¨ Bit 7=0 (always)

Delay= (1+bit6,bit5) ´ 250ms

Typematic rate= 1/period

...where period= (8+A) ´ (2^B) ´ 0.00417

...where A= binary value of bit 2, 1 and 0

...where B= binary value of bit 4 and 3

b4~b0

Typematic

rate

b4~b0

Typematic

rate

00000

30.0

10000

7.5

00001

26.7

10001

6.7

00010

24.0

10010

6.0

00011

21.8

10011

5.5

00100

20.0

10100

5.0

00101

18.5

10101

4.6

00110

17.1

10110

4.3

00111

16.0

10111

4.0

01000

15.0

11000

3.7

01001

13.3

11001

3.3

01010

12.0

11010

3.0

01011

10.9

11011

2.7

01100

10.0

11100

2.5

01101

9.2

11101

2.3

01110

8.6

11110

2.1

01111

8.0

11111

2.0

· Default

¨ delay: 500ms± 20%

¨ typematic rate=10.9 characters/sec± 20%

Commands to the system

00: keyboard detect a error/overrun (set 2, set 3)

AB,83: keyboard ID

AA: BAT completion

FC: BAT failure

EE: Echo

FA: Acknowledge

FE: Resend

FF: Keyboard detects a overrun (set 1)

· FA: Acknowledge

If the KB (Keyboard) receives any valid input except

EE (echo) and resend (FE) then send an FA to the

system first.

If the command is EE, then send an EE back to the

system.

If the command is FE, then send the last key code to

system.

If there is an interrupt while sending FA, the KB dis-

cards the FA and accepts the command from the sys-

tem and processes it.

· 00/FF: Key overrun

If the keyboard detects an overrun error, the KB sends

an overrun error code to the system.

mode 1: FF

mode 2,3: 00

· FE: Resend

The KB issues an FE when there is a parity error in

transmission.

HT82K28A

Data communications

· Data output

¨ If CLK=0, no transmission (keyboard inhibited).

¨ If CLK=1, DATA=0, no transmission (system re-

quest to send).

¨ If CLK=1, DATA=1, transmission permitted.

¨ Data will be valid before the trailing edge and be-

yond the leading edge of the clock.

¨ The KB checks the clock line for an active level at

least every 60ms.

¨ If line contention occurs (system brings the clock

low before the tenth clock), set clock=data=high.

· Data input

¨ The system overrides the clock line for at least

60ms

¨ The keyboard checks the state of the clock line at

intervals of no more than 10ms

¨ If a system request-to-send is detected, the key-

board counts 11 data bits.

¨ Data will be valid before the rising edge and beyond

the falling edge

¨ After the 10th bit, the keyboard checks for an active

level on the ²data² line. If the line is active it is forced

to be inactive, and counts one more bit.

Note:

This action signals the system that the

keyboard has received its data. Upon

reception of this signal, the system returns

to the ready state, in which it can accept

keyboard outputs or goes to the inhibit state

until it is ready.

If the keyboard ²data² line is found to be at an inactive

level following the 10th bit, a frame error has occurred,

and the keyboard continues to count until the ²data²

line becomes active. The keyboard then makes the

²data² line inactive and sends a Resend.

Data stream

B1:

B2:

b3:

b4:

b5:

B6

b7:

b8:

b9:

b10:

b11:

Mode 1,2,3

start bit

always 0

data bit 0

data bit 1

data bit 2

data bit 3

data bit 4

data bit 5

data bit 6

data bit 7

parity bit

(odd par)

stop bit

always 1

Note: The parity bit is either 1 or 0, and the 8 data bits,

plus the parity bit, always have an odd number

of 1¢s.

Rev. 1.30

6

June 27, 2002

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