MSM14Q0230 데이터 시트보기 (PDF) - Oki Electric Industry

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MSM14Q0230

0.35 mm sea of gates arrays

Oki Electric Industry 

s MSM13Q0000/14Q0000 s ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

MSM13Q/14Q FAMILY LISTING

MSM13Q/14Q

Series

0150

0230

0340

0530

0840

1020

PAD No.

144

176

208

256

320

352

Raw Gate

(Gates)

157,192

242,400

346,176

536,400

847,048

1,033,000

Usable Gate

M13Q(3LM)

105,319

152,712

204,244

289,656

415,054

475,180

Usable Gate

M14Q(4LM)

143,045

208,464

276,941

391,572

567,522

650,790

Raw Gate

Row

Column

196

802

240

1,010

288

1,202

360

1,490

452

1,874

500

2,066

ARRAY ARCHITECTURE

The primary components of a 0.35 µm MSM13Q/14Q circuit include:

• I/O base cells

• Configurable I/O pads for VDD, VSS, or I/O (optimized 3-V I/O and 3-V I/O that is 5-V tolerant)

• VDD and VSS pads dedicated to wafer probing

• Separate power bus for output buffers

• Separate power bus for internal core logic and input buffers

• Core base modules containing three compute cells for each drive cell

• Isolated gate structure for reduced input capacitance and increased routing flexibility

Each array has 24 dedicated corner pads for power and ground use during wafer probing, with 4 pads

per corner. The arrays also have separate power rings for the internal core functions (VDDC and VSSC)

and output drive transistors (VDDO and VSSO).

The array architecture uses optimally sized transistors to efficiently implement logic and memory in a

metal programmable technology. CBA uses two types of cells: compute cells and drive cells. The com-

pute cell employs four PMOS and four NMOS trasnsistors whose sizes are optimized for logic and mem-

ory implementations as shown in Figure 1. The quantity and size of the transistors in a compute cell are

carefully selected to maximize the efficiency of most commonly used functions in VLSI design. The drive

cell consists of two large PMOS pull-up transistors and two large pull-down transistors. The compute

and drive cells are tiled to create a channelless core array, with three comput cells for each drive cell as

shown in Figure 2. The 3:1 ratio of compute to drive cells was selected for optimal implementation of

emerging applications. Macrocells are created using either compute cells, drive cells, or combinations of

compute and drive cells.

2

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