P83C180 데이터 시트보기 (PDF) - Unspecified
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P83C180 Datasheet PDF : 84 Pages
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Philips Semiconductors
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
Product specification
P83Cx80; P87C380
6 FUNCTIONAL DESCRIPTION
This chapter gives a brief overview of the device.
Detailed functional descriptions are given in the following
chapters:
Chapter 7 “Memory organization”
Chapter 8 “Interrupts”
Chapter 9 “Watchdog Timer”
Chapter 10 “Input/Output (I/O)”
Chapter 11 “Reduced power modes”
Chapter 12 “Oscillator”
Chapter 13 “Reset”
Chapter 14 “Analog control (DC)”
Chapter 15 “Analog-to-digital converter (ADC)”
Chapter 16 “Digital-to-analog converter (DAC)”
Chapter 17 “Display Data Channel (DDC) interface”
Chapter 18 “I2C-bus Interface”
Chapter 19 “Hardware mode detection”
Chapter 20 “Power management”
Chapter 21 “Control modes”.
6.1 General
The P83C880, P83C180, P83C280, P83C380 and
P87C380 8-bit microcontrollers are manufactured in an
advanced CMOS process and are derivatives of the
80C51 microcontroller family. They have the same
instruction set as the 80C51.
They contain 512 bytes of data memory (RAM). ROM:
8 kbytes (P83C880); 16 kbytes (P83C180); 24 kbytes
(P83C280); 32 kbytes (P83C380) and 16 kbytes of
EPROM for the P87C180. The microcontrollers are
intended for use in monitors ranging from 14" to 21" that
can be controlled from the outside (e.g. by a PC) via the
external DDC interface.
In addition to the 80C51 standard functions, they provide a
number of dedicated hardware functions for monitor
application. Eight general I/O ports plus 20 functions
combined I/O ports cater for application requirements
adequately.
Ten sets of 8-bit PWM deliver the digital waveform for
analog control purposes. One 14-bit PWM can support
F to V application. The keyboard interface is achieved via
a 4-bit ADC. A Watchdog Timer with a maximum count
period of 5 s prevents the processor running out of control
due to malfunction. Four channels of linear DAC with 8-bit
resolution support more accurate analog controls.
One software I2C-bus interface is dedicated for the internal
connection. A DDC interface will cover all DDC protocols,
including DDC1, DDC2B, DDC2AB and DDC2B+.
A hardware mode detector will facilitate mode detection
even in power reduced modes, e.g. Idle mode.
The versatile HSYNC and VSYNC outputs can be
generated to serve the desired application. In the free
running mode, two display patterns can highlight the status
of the monitor. Accordingly, the following items will be
supported by these microcontrollers:
• Mode detection for:
– Horizontal sync (HSYNC) frequencies from below
15 kHz up to 150 kHz
– Vertical sync (VSYNC) frequencies from below 40 Hz
up to 200 Hz
• ACCESS.bus interfacing with external devices, e.g. PCs
• DDC1, DDC2B, DDC2AB and DDC2B+ protocols as
defined in the VESA DDC standard
• Device Power Management Signalling (DPMS) as
described in VESA DPMS proposal.
Figure 1 shows the block diagram functions.
1997 Dec 12
8
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