UP6161 데이터 시트보기 (PDF) - Unspecified

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UP6161

Single 12V Input Supply Dual Regulator Synchronous Buck PWM and Linear Regulator Controller

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Preliminary

uP6161

Functional Description

the uP6161 initiates its digital soft start cycle to prevent

surge current from power supply input during turn on

(referring to the Functional Block Diagram). The error

amplifiers are three-input devices. Reference voltage VREF

or the internal soft start voltage SS2/SS3 whichever is

smaller dominates the behavior of the non-inverting inputs

of the error amplifiers. SS2/SS3 internally ramps up to 0.8V

in 4096 cycles of the internal oscillator frequency after the

after the softstart cycle is initiated. Take 600kHz switching

frequency for example (1.67us per cycle), the ramp-up time

is about 6.8ms. Accordingly, the output voltages follow the

soft start signals SS2/SS3 and linearly ramp up to their

final level, resulting minimum inrush current from input

voltage.

The SS2/SS3 signals keep ramping up after it exceeds

the internal 0.8V reference voltages. However, the internal

0.8V reference voltages takes over the behavior of error

amplifier after SS > VREF. When the SS2/SS3 signal climb

to its ceiling voltage (5V), the uP6161 claims the end of

softstart cycle and enable the under voltage protection of

the output voltages.

Figure 3 shows a typical start up interval for uP6161 where

the RT/DIS pin has been released from a grounded (system

shutdown) state. Note the LDO output voltage (LVO)

starts ramping up only after the PWM output voltage

(SVO) is within regulation.

RT/DIS

(1V/Div)

SVO

(0.5V/Div)

LVO

(0.5V/Div)

ramping up to 5VDD. Another softstart is initiated after SS

ramps up to 5VDD. The hiccup period is about 8ms. Figure

4 shows the start up interval where V does not present

IN

initially.

VIN

(5V/Div)

SVO

(0.5V/Div)

LVO

(0.5V/Div)

LGATE

(10V/Div)

Time (5ms/Div)

Figure 4. Softstart where V does not Present Initially.

IN

Output Voltage Selection

The output voltage can be programmed to any level between

the 0.8V internal reference, up to the 80% of V supply.

IN

The lower limitation of output voltage is caused by the

internal reference. The upper limitation of the output voltage

is caused by the maximum available duty cycle (80%

typical). This is to leave enough time for overcurrent

detection. Output voltage out of this range is not allowed.

A voltage divider sets the output voltage (refer to the Typical

Application Circuit on page 1 for detail). In real applications,

choose R2 in 100Ω ~ 10kΩ range and choose appropriate

R1 according to the desired output voltage.

VOUT

=

VREF

×

R1+ R2

R2

=

0.8V ×

R1+ R2

R2

PHASE

(10V/Div)

Time (5ms/Div)

Figure 3. Softstart Behavior.

Power Input Detection

The uP6161 detects PHASE voltage for the present of power

input when the UGATE turns on the first time. If the PHASE

voltage does not exceed 2.0V when the UGATE turns on,

the uP6161 asserts that power input in not ready and stops

the softstart cycle. However, the internal SS continues

Overcurrent Protection (OCP)

The uP6161 detects voltage drop across the lower MOSFET

(VPHASE) for overcurrent protection when it is turned on. If

VPHASE is lower than the user-programmable voltage VOCP,

the uP6161 asserts OCP and shuts down the converter.

The OCP level can be calculated according the on-

resistance of the lower MOSFET used.

IOCP

=

− VOCP

RDS(ON)

(A)

Connecting a resistance from LGATE to GND selects the

uPI Semiconductor Corp., http://www.upi-semi.com

6

Rev. P00, File Name: uP6161-DS-P0001

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