AD9911(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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AD9911 Datasheet PDF : 44 Pages
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GENERAL DESCRIPTION
The DDS acts as a high resolution frequency divider with the
REF_CLK as the input and the DAC providing the output. The
REF_CLK input can be driven directly or used in combination
with an integrated REF_CLK multiplier (PLL). The REF_CLK
input also features an oscillator circuit to support an external
crystal as the REF_CLK source. The crystal can be used in
combination with the REF_CLK multiplier.
The AD9911 I/O port offers multiple configurations to provide
significant flexibility. The I/O port offers an SPI-compatible
mode of operation that is virtually identical to the SPI operation
found in earlier Analog Devices DDS products.
AD9911
Flexibility is provided by four data pins (Pin SDIO_0,
Pin SDIO_1, Pin SDIO_2, and Pin SDIO_3) that allow four
programmable modes of I/O operation.
The DAC output is supply referenced and must be terminated
into AVDD by a resistor and an AVDD center-tapped trans-
former. The DAC has its own programmable reference to enable
different full-scale currents.
The DDS core (the AVDD pins and the DVDD pins) is powered
by a 1.8 V supply. The digital I/O interface (SPI) operates at
3.3 V and requires that the Pin DVDD_I/O (Pin 49) be
connected to 3.3 V.
FUNCTIONAL BLOCK DIAGRAM
AD9911
32 Σ
32
FTW/ 32
ΔFTW
Σ
Σ 15 COS(X) 10
10 Σ
DAC
PHASE/ 14
ΔPHASE
AMP/ 10
ΔAMP
SCALABLE
DAC REF
CURRENT
SPURKILLER/
MULTI-TONE
DDS
CORE
MUX
DDS DDS
CORE CORE
SYNC_IN
SYNC_OUT
I/O_UPDATE
SYNC_CLK
REF_CLK
REF_CLK
TIMING AND CONTROL LOGIC
SYSTEM
÷4
CLK
BUFFER/
XTAL
OSCILLATOR
REF CLOCK
MULTIPLIER
4× TO 20×
MUX
1.8V
1.8V
CONTROL
REGISTERS
CHANNE L
REGISTERS
PROFILE
REGISTERS
CLK_MODE_SEL
LOOP FILTER
AVDD DVDD
P0 P1 P2 P3
Figure 2. Functional Block Diagram
I/O
PORT
BUFFER
3.3V
DVDD_I/O
IOUT
IOUT
DAC_RSET
PWR_DWN_CTL
MASTER_RESET
SCLK
CS
SDIO_0
SDIO_1
SDIO_2
SDIO_3
Rev. 0 | Page 3 of 44
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